Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/26/2023
Public

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6.6. Reset Interfaces

Reset interfaces provide both soft and hard reset functionality. Soft reset logic typically re-initializes registers and memories without powering down the device. Hard reset logic initializes the device after power-on.

You can define separate reset sources for each clock domain, a single reset source for all clocks, or any combination in between. You can choose to create a single global reset domain by clicking System > Create Global Reset Network. If your design requires more than one reset domain, you can implement your own reset logic and connectivity. The IP Catalog includes a reset controller, reset sequencer, and a reset bridge to implement the reset functionality. You can also design your own reset logic.

Platform Designer interconnect now supports synchronous reset of registers in the interconnect. Use of synchronous reset can result in higher performance for Intel® Stratix® 10 designs because although Intel® Stratix® 10 Hyper-Registers lack a reset signal, they can make use of the synchronous reset from an adjacent LAB. If a register in your Intel® Stratix® 10 design uses asynchronous reset, the Compiler cannot implement the register as a Hyper-Register, potentially reducing performance.

When Use synchronous reset is set to True in the Domains tab, all registers in the interconnect use synchronous reset. The Use synchronous reset option is enabled by default for Intel® Stratix® 10 designs, but is disabled by default for all other designs.

Note: If you design your own reset circuitry, you must carefully consider situations which may result in system lockup. For example, if an Avalon® memory mapped agent is reset in the middle of a transaction, the Avalon® memory mapped host may lockup.