CPRI Intel® FPGA IP User Guide

ID 683595
Date 10/07/2022

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Document Table of Contents Tx Path Delay

The Tx path delay is the cumulative delay from the arrival of the first bit of a 10 ms radio frame on the CPRI AUX interface (or other direct interface) to the start of transmission of this data on the CPRI link.
Figure 61. Tx Path Delay from AUX Interface to CPRI Link in CPRI Intel® FPGA IP Core

The Tx path delay from the AUX interface to the CPRI link is the sum of the following delays:

  1. Fixed delay from the AUX interface though the CPRI low-level transmitter to the Tx elastic buffer. This delay depends on the device family and the current CPRI line bit rate.
  2. Variable delay through the Tx elastic buffer, as well as the phase difference between the core clock cpri_clkout and the transceiver tx_clkout clock. The "Extended Delay Measurement" section shows how to calculate the delay in the CPRI Intel® FPGA IP Tx elastic buffer, which includes the phase difference delay.
  3. Variable Tx bitslip delay in CPRI RE slaves. Refer to "Tx Bitslip Delay."
  4. Fixed delay from the Tx elastic buffer to the transceiver. This delay depends on the device family and the CPRI line bit rate.
    Note: In Intel® FPGA IP core variations that target an Intel® Stratix® 10 device, you must also add the delay through the Stratix 10 hard FIFOs in the Tx path. Refer to "Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs" section.
  5. Link delay through the transceiver.