CPRI Intel® FPGA IP User Guide

ID 683595
Date 10/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.17.1. Extended Delay Measurement for Soft Internal Buffers

The CPRI Intel® FPGA IP uses a dedicated clock, ex_delay_clk, to measure the delay through the RX and TX internal buffers to your desired precision. The extended delay process is identical for the two directions of flow through the IP core; the TX_EX_DELAY and RX_EX_DELAY registers hold the same information for the two directions.

The tx_msrm_period field of the TX_EX_DELAY register contains the value N, such that N clock periods of the ex_delay_clk clock are equal to some whole number M of cpri_clkout periods. For example, N may be a multiple of M, or the M/N frequency ratio may be slightly greater than 1, such as 64/63 or 128/127. The application layer specifies N to ensure the accuracy your application requires. The accuracy of the Tx buffer delay measurement is N/least_common_multiple(N,M) cpri_clkout periods.

Similarly, the rx_msrm_period field of the RX_EX_DELAY register contains the value N, such that N clock periods of the ex_delay_clk clock are equal to some whole number M of cpri_clkout periods.

If your application does not require this precision, drive the ex_delay_clk input port with the cpri_clkout signal. In this case, the M/N ratio is 1 because the frequencies are the same.

The tx_buf_delay field of the TX_DELAY register indicates the number of 32-bit words currently in the Tx buffer. After you program the tx_msrm_period field of the TX_EX_DELAY register with the value of N, the tx_ex_delay field of the TX_EX_DELAY register holds the current measured delay through the Tx buffer. The unit of measurement is cpri_clkout periods. The tx_ex_delay_valid field indicates that a new measurement has been written to the tx_ex_delay field since the previous register read. The following sections explain how you set and use these register values to derive the extended Tx delay measurement information.

M/N Ratio Selection

As your selected M/N ratio approaches 1, the accuracy provided by the extended delay measurement increases.

Table 37.  Resolution as a Function of M/N Ratio at 3.072 Gbps
M N cpri_clkout Period ex_delay_clk Period Resolution
128 127 13.02 ns (1/76.80 MHz) 13.12 ns ±100 ps
64 63 13.22 ns ±200 ps
1 4 3.25 ns ±3.25 ns

Extended Delay Measurement Calculation Example

This section walks you through an example that shows you how to calculate the frequency at which to run ex_delay_clk, and how to program and use the registers to determine the delay through the CPRI Receive Buffer.

For example, assume your CPRI Intel® FPGA IP runs at CPRI line bit rate 3.072 Gbps. In this case, the cpri_clkout frequency is 76.80, so a cpri_clkout cycle is 1/76.80 MHz.

If your accuracy resolution requirements are satisfied by an M/N ratio of 128/127, perform the following steps:

  1. Program the value N=127 in the rx_msrm_period field of the RX_EX_DELAY register at offset 0x54.
  2. Perform the following calculation to determine the ex_delay_clk frequency that supports your desired accuracy resolution:

    ex_delay_clk period = (M/N) cpri_clkout period = (128/127)(1/(76.80 MHz)= 13.123356 ns.

    Based on this calculation, the frequency of ex_delay_clk is 1/(13.123356 ns)

    The following steps assume that you run ex_delay_clk at this frequency.

  3. Read the value of the RX_EX_DELAY register at offset 0x54.

    If the rx_ex_delay_valid field of the register is set to 1, the value in the rx_ex_delay field has been updated, and you can use it in the following calculations. For this example, assume the value read from the rx_ex_delay field is 0x107D, which is decimal 4221.

  4. Perform the following calculation to determine the delay through the Rx buffer:

    Delay through Rx buffer = (rx_ex_delay x cpri_clkout period) / N = (4221 x 13.02083 ns) / 127 = 432.7632 ns.

    This delay comprises (432.7632ns / 13 .02083 ns) = 33.236 cpri_clkout clock cycles.

These numbers provide you the result for this particular example. For illustration, the preceding calculation shows the result in nanoseconds. You can derive the result in cpri_clkout clock cycles by dividing the preceding result by the cpri_clkout clock period. Alternatively, you can calculate the number of cpri_clkout clock cycles of delay through the Rx buffer directly, as rx_msrm_period/N.