CPRI Intel® FPGA IP User Guide

ID 683595
Date 10/07/2022

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Document Table of Contents Single-Trip Delay Calibration

The CPRI Intel® FPGA IP provides an optional mechanism to support calibrating the total delay through a CPRI master and slave on the downlink in a single hop.

If you turn on Enable single-trip delay calibration in the CPRI parameter editor, the CPRI IP and IOPLL and dynamic phase control unit (DPCU) blocks work together to adjust the delay through the RE slave Rx path in response to information about the delay through the REC or RE master Tx path.

Figure 62. Downlink Slave Delay Adjustment for Single-Trip Delay Calibration

The feature introduces the new delay to maintain a single-trip delay measurement as close as possible to the desired single-trip delay you provide to the CPRI IP. The application can also provide Tx path delay information that is appropriate for other use scenarios. For example, you might want to adjust the latency to the synchronization SAP to compensate for the IQ mapper requirements in your system. Refer to the Intel FPGA Wiki CPRI Intel® FPGA IP v6 Latency Formula and Calculation Example.

Figure 63. Single-Trip Delay Does Not Affect Link Delay

The cal_cycle_delay and cal_step_delay fields of the DELAY_CAL_STD_CTRL2 register in the CPRI link slave hold the anticipated delay that you program. The cal_current_delay field of the DELAY_CAL_STD_STATUS register in the CPRI link slave holds the total actual variable delay measurement in the single trip from the synchronization SAP in the CPRI link master to the synchronization SAP in the current CPRI link slave. You can manually specify a consistency check whenever you want, or you can specify that the IP core should run a consistency check once every hyperframe.

If you turn on single-trip delay calibration by setting the cal_en bit in the DELAY_CAL_STD_CTRL1 register, the single-trip calibration feature is active. The user programs the cal_cycle_delay and cal_step_delay fields with the number of whole and fractional cpri_clkout cycles of single-trip variable delay that the system requires. After each consistency check, the CPRI slave IP core adjusts the Rx delay to compensate for mismatches between the programmed, required single-trip delay and the actual single-trip variable delay recorded in the cal_current_delay register field. The delay adjustment mechanism is dynamic phase shifting of the cpri_coreclk.

The slave IP core requires the master IP core measured Tx delay information to calculate the cal_current_delay value. The master IP core sends this information to its downlink slave by one of two possible mechanisms. You program the master IP core DELAY_CAL_STD4 register to specify whether the master sends this information in the incoming hyperframe (and at which location in the hyperframe) or the system writes it in the dedicated slave IP core DELAY_CAL_STD_CTRL5 register. You program the slave IP core DELAY_CAL_STD3 register to specify whether the slave receives this information in the incoming hyperframe (and at which location in the hyperframe) or the system writes it in the dedicated slave DELAY_CAL_STD_CTRL5 register. If both CPRI master and slave are CPRI IP cores, and the register values in the CPRI link master and slave do not match, the single-trip delay calibration does not function correctly. If the CPRI master is not a CPRI IP, the CPRI slave must receive the correct information in the programmed register or hyperframe location.