CPRI Intel® FPGA IP User Guide

ID 683595
Date 10/07/2022

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2.5.4. Adding the Transceiver Reconfiguration Controller

CPRI Intel® FPGA IP cores that target Arria V, Arria V GZ, Cyclone V, and Stratix V devices require an external reconfiguration controller to compile and to function correctly in hardware. CPRI IP cores that target Intel® Arria® 10 or Intel® Stratix® 10 devices include a transceiver reconfiguration controller block and do not require an external reconfiguration controller.

You can use the IP Catalog to generate the Transceiver Reconfiguration Controller Intel FPGA IP core required for Arria V, Arria V GZ, Cyclone V, and Stratix V designs.

When you configure the Transceiver Reconfiguration Controller, you must specify the number of reconfiguration interfaces. The number of reconfiguration interfaces required for the CPRI IP core depends on the CPRI IP core configuration and your design.For example, you can configure your reconfiguration controller with additional interfaces if your design connects with multiple transceiver IP cores. You can leave other options at the default settings or modify them for your preference. Refer to the V-Series Transceiver PHY User Guide.

You should connect the reconfig_to_xcvr and reconfig_from_xcvr ports of the CPRI IP core to the corresponding ports of the reconfiguration controller.

You must drive the CPRI IP core reconfig_clk input port and the Transceiver Reconfiguration Controller mgmt_clk_clk input port from the same clock source. Drive both ports at a clock frequency in the range of 100–150MHz.