E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 5/25/2023

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3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example

After you compile the E-tile CPRI PHY Intel® FPGA IP core design example and configure it on your Intel® Stratix® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main_script.tcl to open a connection to the JTAG master and start the test.

    You can program the IP core with the following design example commands:

    The following sample output illustrates a successful test run for 10.1376 Gbps CPRI line bit rate with 1 CPRI channel:
    source main_script.tcl
    Info: Number of Channels = 1
    Info: JTAG Port ID = 0
    Info: Speed = 10G
    Info: Start of c3 cpri test
    Info: Basic CPRI test 
    INF0: Checking PLL Lock status... 
    	  iopll_sclk_Locked I,channel_pll_locked I 
    INF0: PLL is Locked 
    INF0: Set Reconfig Reset 
    INF0: Release Reconfig Reset
    INF0: Release CSR Reset 
    INF0: Release TX Reset
    INF0: Release RX Reset
    INF0: Release Reset Done!
    INF0: Turn on serial Loopback
    		INFO: Start of C3 ELANE XCVR Channel O Loopback mode
    		INFO: Pooling for PMA Register: Read XCVR CSR Register offest = 0x8a, data= 0x84
    		INFO: Pooling for PMA Register: Read XCVR CSR Register offest = 0x8b, data= 0x8e
    		INFO: C3 ELANE XCVR Channel 0 Loopback mode is successfult enabled 
    Loop 0
    Channel 0 : Wait for measure_valid to assert
    Channel 0 : Get checker_pass status:
    			Checker value = 1
    			Checker status = Passed!
    Channel 0 : Read Deterministic latency counts
    Info: Loop 0 passed
    End of loop 0
    Info: End of c3_cpri_test
    Info: Test <c3_cpri_test> Passed