E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 5/25/2023

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2.2.3. 10GE/25GE Design Example Interface Signals

The following signals are hardware design example signals for all 10GE/25GE variants.

Table 6.  10GE/25GE Hardware Design Example Interface Signals
Signal Direction Description
clk100 Input Drive at 100 to 161.13 MHz. Input clock for CSR access on all the AVMM interfaces.
i_clk_ref Input Drive at 322.265625 MHz.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
o_tx_serial[(number of channels-1:0] Output Transceiver PHY output serial data.
i_rx_serial[number of channels-1:0] Input Transceiver PHY input serial data.