E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 5/25/2023

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Document Table of Contents Fast Sim Model for E-tile Ethernet IP for Intel Stratix 10 FPGA

To provide a reduction in a real-time simulation duration, you can utilize a Fast Sim model in your design example testbench. The model is enabled by a macro in the simulation run script.
To enable the Fast Sim model, add the following macro to your simulation run script:

The design example simulation script does not enable the macro by default for any variants. You need to manually add the macro. The Fast Sim Model is supported in variants without PTP, auto-negotiation and link training, or dynamic reconfiguration enabled.

  • In PTP variants, the macro is disabled by default as it affects the timestamp accuracy in simulation. If you want to perform a general functionality check, you can enable the macro in your PTP simulation scripts.
  • The macro can cause the testbench to fail in designs with enabled auto-negotiation and link training, or dynamic reconfiguration.
Note: Only Synopsys VCS, Siemens EDA ModelSim SE, and QuestaSim support the Fast Sim Model.

You can also add the macro to your simulation script for your own testbench.