E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 5/25/2023

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2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench

Figure 4. Procedure

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the following table: Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench sends ten or fourteen packets, receives the same number of packets, and displays "Testbench complete."
    Table 4.  Steps to Simulate the Testbench
    Simulator Instructions
    Siemens* EDA ModelSim* SE or QuestaSim* In the command line, type vsim -do run_vsim.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do

    Note: The Questa* Intel® FPGA Edition simulator does not have the capacity to simulate this IP core. You must use ModelSim* SE or QuestaSim* .
    Synopsys* VCS* / VCS* MX In the command line, type sh run_vcs.sh or sh run_vcsmx.sh
    Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.
    Xcelium* In the command line, type sh run_xcelium.sh