E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 5/25/2023

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3.2.3. Hardware Design Example

Figure 30.  E-tile CPRI PHY Intel® FPGA IP Core Hardware Design Examples High Level Block Diagram
The E-tile CPRI PHY Intel® FPGA IP core hardware design example includes the following components:
  • E-tile CPRI PHY Intel® FPGA IP core.
  • Packet client logic block that generates and receives traffic.
  • Round trip counter.
  • IOPLL to generate sampling clock for deterministic latency logic inside the IP, and round trip counter component at testbench.
  • Channel PLL to generate external AIB clocks for the IP.
  • Avalon® -MM address decoder to decode reconfiguration address space for CPRI, transceiver, and RS-FEC modules during reconfiguration accesses.
  • Sources and probes for asserting resets and monitoring the clocks and a few status bits.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.
  • The example design targets an Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.