E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 5/25/2023

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4.2.4. 10GE/25GE Design Example Interface Signals

The following signals are hardware dynamic reconfiguration design example signals for all 10GE/25GE variants.

Table 29.  10GE/25GE Dynamic Reconfiguration Design Example Hardware Design Example Interface Signals
Signal Direction Comments
clk100 Input Input clock for reconfiguration. Drive at 100 MHz. The intent is to drive this from a 100 Mhz oscillator on the board.
cpu_resetn Input Global reset for Nios® II system.
i_clk_ref 4 Input Reference clock 25G IP core. Drive at 156.25MHz.
o_tx_serial Output Transmit serial data.
i_rx_serial Input Receiver serial data.
4 i_clk_ref is also used in the 25G + RS-FEC design to provide clock to to a PMA direct module, which acts as a channel PLL to supply the required E-tile Ethernet TX/RX clocks and EMIB clocks.