E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 9/26/2022

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3.1.2. Generating the Design

Example Design Tab in the E-tile CPRI PHY Intel® FPGA IP Parameter Editor
If you do not already have an Intel® Quartus® Prime Pro Edition project in which to integrate your E-Tile Hard IP for Ethernet Intel FPGA IP IP core, you must create one.
  1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Intel Stratix 10 and select a device that meets all of these requirements:
    • Transceiver tile is E-tile
    • Transceiver speed grade is -1 or -2
    • Core speed grade is -1 or -2
  3. Click Finish.
Follow these steps to generate the E-tile CPRI PHY IP hardware design example and testbench:
  1. In the IP Catalog, locate and select E-tile CPRI PHY Intel® FPGA IP . The New IP Variation window appears.
  2. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  3. Click OK. The parameter editor appears.
  4. On the IP tab, specify the parameters for your IP core variation.
  5. The hardware design example provided with enable internal serial loopback by default.
  6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  7. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL. If you select VHDL, you must simulate the testbench with a mixed-language simulator. The device under test in the ex_<datarate> directory is a VHDL model, but the main testbench file is a System Verilog file.
  8. Under Target Development Kit, select the Stratix 10 TX Transceiver Signal Integrity Development Kit or select None. The compilation-only and hardware design examples target your project device. For the hardware design to function correctly, you must ensure that your project device is the same device on your development kit.
  9. Click the Generate Example Design button. The Select Example Design Directory window appears.
  10. If you want to modify the design example directory path or name from the defaults displayed (alt_cpriphy_c3_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).