E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 9/26/2022
Public

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4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components

The 10GE/25GE hardware dynamic reconfiguration design example includes the following components:
  • E-Tile Hard IP for Ethernet Intel FPGA IP core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • Time-of-day (ToD) module to provide a continuous flow of current time-of-day information to the IP core.
  • PIO block to store RX and TX PTP timestamp for accuracy calculation and to send PTP 2-step timestamp request.
  • Avalon® -MM address decoder to decode reconfiguration address space for MAC, transceiver, and RS-FEC modules during reconfiguration accesses.
  • Nios® II System that communicates with the Nios® II Software Build Tools (SBT) for Eclipse. You communicate with the client logic and E-Tile Hard IP for Ethernet Intel FPGA IP through the tool.
  • Triple-Speed Ethernet Intel FPGA IP .
  • IO PLL to provide datapath clocks 62.5 MHz and 125 MHz as required by the Triple-Speed Ethernet Intel FPGA IP.
  • E-tile CPRI PHY EFIFO to handle the clock-crossing between the Triple-Speed Ethernet Intel FPGA IP and Native PHY's PMA.
  • ToD master module to provide a continuous flow of current time-of-day information to Triple-Speed Ethernet Intel FPGA IP.
  • Ethernet 1GE packet generator and monitor for Triple-Speed Ethernet Intel FPGA IP packet generation and monitoring.
By default, the hardware test run uses the internal serial loopback mode. The following sample outputs illustrate a successful hardware test run for a 25GE, MAC+PCS, RS-FEC, with PTP IP core variation. The hardware test uses this user control GUI to switch to any supported mode.
CPU is alive!


             Dynamic Reconfiguration Hardware Test

By default, the starting mode is 25G_PTP_FEC.
      Please choose one of Dynamic reconfiguration:
    0) 25G_PTP_FEC    -> 25G_PTP_noFEC -> 10G_PTP -> 25G_PTP_noFEC -> 25G_PTP_FEC -> 10G_PTP -> 25G_PTP_FEC
-> 1G_PTP -> 10G_PTP -> 1G_PTP -> 25G_PTP_noFEC -> 1G_PTP -> 25G_PTP_FEC
    1) 25G_PTP_FEC    -> 25G_PTP_noFEC
    2) 25G_PTP_noFEC  -> 25G_PTP_FEC
    3) 25G_PTP_FEC    -> 10G_PTP
    4) 10G_PTP        -> 25G_PTP_FEC
    5) 25G_PTP_noFEC  -> 10G_PTP
    6) 10G_PTP        -> 25G_PTP_noFEC
    7) 25G_PTP_FEC    -> 1G_PTP
    8) 1G_PTP         -> 25G_PTP_FEC
    9) 10G_PTP        -> 1G_PTP
    a) 1G_PTP         -> 10G_PTP
    b) 25G_PTP_noFEC  -> 1G_PTP
    c) 1G_PTP         -> 25G_PTP_noFEC
       Terminate test
       If you terminate test halfway, you must reload the .sof file before retrigger the hardware test.

Enter a Valid Selection (0,1,3,7,d):