E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 9/26/2022

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4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals

The following signals are hardware dynamic reconfiguration design example signals for 100G Ethernet Dynamic Reconfiguration variants.

Table 51.  100G Ethernet Dynamic Reconfiguration Design Example Hardware Interface Signals
Signal Direction Comments
clk100 Input Input clock for reconfiguration. Drive at 100 MHz. The intent is to drive this from a 100 Mhz oscillator on the board.
cpu_resetn Input Input reset for the dynamic reconfiguration controller.
i_csr_rst_n   Resets the entire IP core.
refclk Input 156.25 MHz clock for the 100G Ethernet IP core..
o_tx_serial Output Transmit serial data.
i_rx_serial Input Receiver serial data.