E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 9/26/2022

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Document Table of Contents

3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.11.22 21.3 19.5.0
  • Added support for QuestaSim* simulator.
  • Removed support for NCSim simulator.
2020.12.14 19.4 19.4.0 Added a reference link to Simulating the Design Example Testbench topic in section Simulation Design Example.
2020.04.13 19.4 19.4.0 Added support for 3.0720, 6.1440, and 10.1376 (with RS-FEC) Gbps CPRI line rates.
2019.08.07 19.2 19.2.0
  • Added Figure: E-tile CPRI PHY Intel FPGA IP Simulation Block Diagram for 2.4/4.9/9.8 Line Rates.
  • Updated E-tile CPRI PHY Intel FPGA IP Core Hardware Design Examples High Level Block Diagram for new supported CPRI line rates.
  • Added the frequency value for the 2.4/4.8/9.8 Gbps line rates in section Compiling and Configuring the Design Example in Hardware.
  • Clarified i_clk_ref frequency value for different CPRI line rates.
2019.05.17 19.1 19.1 Initial release.