E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 9/26/2022
Public

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2.3. 100GE with Optional RS-FEC Design Example

The 100GE design example demonstrates an Ethernet solution for Intel® Stratix® 10 devices using the E-Tile Hard IP for Ethernet Intel FPGA IP core with the following variants:
Table 10.  Supported Design Example Variants for 100GE
Variant Design Example Support

Non-PTP MAC+PCS with Optional RS-FEC (528,514)/(544,514)

  • For (528,514) RS-FEC variant, the design example consists of 4 transceiver channels
  • For (544,514) RS-FEC variant, the design example consists of 2 transceiver channels
Simulation, compilation-only project, and hardware design example

MAC+PCS with Optional RS-FEC and PTP (528,514)

  • For (528,514) RS-FEC variant, the design example consists of 4 transceiver channels
Simulation, compilation-only project, and hardware design example

PCS Only with Optional RS-FEC (528,514)/(544,514)

  • For (528,514) RS-FEC variant, the design example consists of 4 transceiver channels
  • For (544,514) RS-FEC variant, the design example consists of 2 transceiver channels
Simulation, compilation-only project, and hardware design example

OTN with Optional RS-FEC (528,514)/(544,514)

  • For (528,514) RS-FEC variant, the design example consists of 4 transceiver channels
  • For (544,514) RS-FEC variant, the design example consists of 2 transceiver channels
Simulation and compilation-only project

FlexE with Optional RS-FEC (528,514)/(544,514)

  • For (528,514) RS-FEC variant, the design example consists of 4 transceiver channels
  • For (544,514) RS-FEC variant, the design example consists of 2 transceiver channels
Simulation and compilation-only project
Note: The E-Tile Hard IP for Ethernet Intel FPGA IP provides support for the OTN feature. For further inquiries, contact your nearest Intel sales representative.