Intel® FPGA Programmable Acceleration Card D5005 Data Sheet
ID
683568
Date
11/04/2019
Public
2.1. Intel® FPGA PAC D5005 Specifications
Figure 1. Conceptual Block Diagram
| Specification | Value |
|---|---|
| Power | 215 W (Under sufficient cooling capabilities) 1 |
| Cooling Requirement | Passively cooled. Requires server air flow. |
| Weight | 1 Kilogram |
| Form Factor | ¾ Length, Full height, Dual-slot PCIe* 3.0 CEM specification compliant |
| Networking Interfaces | Dual QSFP28 Ports: 2x100G |
| Memory Interfaces | 4x 8GB DDR4-2400 with ECC |
| Management Port | Micro-USB |
| FPGA Device | 1SX280HN2F43E2VG |
Note: Initially 1x10G and 4x10G networking capability is supported on each QSFP28 port. Additional configurations will be supported in future releases.
1 65 W from the 12 V slot and 150 W from 12 V 2x4 pin auxiliary power connector. 10 W from the 3.3 V slot is not used.