Intel® FPGA Programmable Acceleration Card D5005 Data Sheet

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ID 683568
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Board Management Controller 4. FPGA Interface Manager 5. System Compatibility 6. Power Requirements 7. Mechanical Information 8. Thermal and Airflow Requirements A. Safety and Regulatory Information B. Revision History
2. Overview x
2.1. Intel® FPGA PAC D5005 Specifications 2.2. Intel® FPGA PAC Components
2.2. Intel® FPGA PAC Components x
2.2.1. Intel® Stratix® 10 FPGA 2.2.2. Power 2.2.3. PCIe* Interface 2.2.4. DDR4 SDRAM 2.2.5. Network Interface 2.2.6. Field Replaceable Unit Identification EEPROM 2.2.7. MAC Address EEPROM 2.2.8. Flash Memory 2.2.9. Control and Support
3. Board Management Controller x
3.1. Health Monitoring Features 3.2. Supported PLDM/MCTP Commands
7. Mechanical Information x
7.1. Ports and LEDs
8. Thermal and Airflow Requirements x
8.1. Thermal Cooling Requirements 8.2. Airflow Requirements
A. Safety and Regulatory Information x
A.1. Regulatory Compliance
1. Introduction
2. Overview
3. Board Management Controller
4. FPGA Interface Manager
5. System Compatibility
6. Power Requirements
7. Mechanical Information
8. Thermal and Airflow Requirements
A. Safety and Regulatory Information
B. Revision History

7.1. Ports and LEDs

Various status LEDs are provided at the front panel to indicate the Intel® FPGA PAC operating condition. The I/O panel status LED indicators are defined below.

Figure 6. Ports and LEDs

Port Description

  • Network Port 0 – QSFP28 port capable of accepting 40 Gbps/100 Gbps SR optical module or 3 meter DAC cable
  • Network Port 1 – QSFP28 port capable of accepting 40 Gbps/100 Gbps SR optical module or 3 meter DAC cable
Table 9.  I/O Panel Definition
LED Name Description
12V Orange LED. On when 12 V power source is present. Off if 12V power source is not present.
PG Orange LED. On when board power is present. Off if board power is not present.
DONE

Green LED. On indicates that the FPGA FIM is successfully loaded. This LED does not change states when AFUs are loaded.

FPGA LED 3 Green LED. Connected to FPGA for workload usage. State of LED is defined by the configured workload.
FPGA LED 2 Green LED. Connected to FPGA for workload usage. State of LED is defined by the configured workload.
FPGA LED 1 Green LED. Connected to FPGA for workload usage. State of LED is defined by the configured workload.
FPGA LED 0 Green LED. Connected to FPGA for workload usage. State of LED is defined by the configured workload.
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