Intel® FPGA Programmable Acceleration Card D5005 Data Sheet

ID 683568
Date 11/04/2019
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1. Introduction

The Intel FPGA Programmable Acceleration Card D5005 ( Intel® FPGA PAC D5005) is a PCI Express* Gen 3 x16 compliant card designed to accelerate data center applications.

This datasheet for the Intel® FPGA PAC shows electrical, mechanical, compliance, and other key specifications. This datasheet assists data center operators and system integrators to properly deploy the Intel® FPGA PAC into their servers. It also documents the FPGA power envelope, connectivity speeds to memory, and network connectivity, so that accelerator function unit (AFU) developers can properly design and test their IP.

The Intel® FPGA PAC is supported by the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs. The Acceleration Stack provides a common developer interface to both application and accelerator function developers and includes drivers, Application Programming Interfaces (APIs) and an FPGA Interface Manager (FIM).

Along with acceleration libraries and development tools, the Acceleration Stack saves development time and enables code re-use across multiple Intel FPGA form-factor products, allowing the developer to focus on the unique value-addition of their solution. Developers can use the Accelerator Functional Unit (AFU) Developer's User Guide to get started.

Intel validates each Intel® FPGA PAC to support large scale deployments requiring FPGA acceleration.

This platform is targeted for market-specific acceleration in applications such as:
  • Finance
  • Data Analytics
  • Video Transcoding
  • Genomics
  • Cyber-Security
  • High-Performance Computing
  • Artificial Intelligence
Note: Throughout this document, any mention of Intel® FPGA PAC or Intel® FPGA PAC D5005 shall specifically refer to the Intel FPGA Programmable Acceleration Card D5005.