Intel® FPGA Programmable Acceleration Card D5005 Data Sheet

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ID 683568
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Board Management Controller 4. FPGA Interface Manager 5. System Compatibility 6. Power Requirements 7. Mechanical Information 8. Thermal and Airflow Requirements A. Safety and Regulatory Information B. Revision History
2. Overview x
2.1. Intel® FPGA PAC D5005 Specifications 2.2. Intel® FPGA PAC Components
2.2. Intel® FPGA PAC Components x
2.2.1. Intel® Stratix® 10 FPGA 2.2.2. Power 2.2.3. PCIe* Interface 2.2.4. DDR4 SDRAM 2.2.5. Network Interface 2.2.6. Field Replaceable Unit Identification EEPROM 2.2.7. MAC Address EEPROM 2.2.8. Flash Memory 2.2.9. Control and Support
3. Board Management Controller x
3.1. Health Monitoring Features 3.2. Supported PLDM/MCTP Commands
7. Mechanical Information x
7.1. Ports and LEDs
8. Thermal and Airflow Requirements x
8.1. Thermal Cooling Requirements 8.2. Airflow Requirements
A. Safety and Regulatory Information x
A.1. Regulatory Compliance
1. Introduction
2. Overview
3. Board Management Controller
4. FPGA Interface Manager
5. System Compatibility
6. Power Requirements
7. Mechanical Information
8. Thermal and Airflow Requirements
A. Safety and Regulatory Information
B. Revision History

8. Thermal and Airflow Requirements

The Intel® FPGA PAC D5005 has been thermally validated to 189 W for the entire card under provided flow characteristics. The FPGA junction temperature must not exceed 100 °C. The temperature of the QSFP28 modules must meet the module vendor’s specification, typically 70 °C or 85 °C.

Table 10.  Thermal Specifications
Parameter Value
Operating Temperature 0 °C – 45 °C
Storage Temperature -40 °C to 65 °C
Storage Humidity 5% to 85% RH with a 35 °C (95 °F) maximum dew point
Note: The BMC continuously monitors the FPGA junction temperature and will automatically shut down the Intel® FPGA PAC D5005 when the FPGA junction temperature reaches 100 °C.
Note: AFU Developers should use the Intel Stratix 10 PowerPlay Early Power Estimator and the Quartus Prime Power Analyzer to estimate the FPGA power consumption.
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