R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 6/20/2022

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Document Table of Contents Xcelium* Simulator

Note: Xcelium* simulator support is only available in devices with the suffix R2 or R3 in their OPN numbers. For more details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.
Perform the following steps to execute the simulation via a command line:
  1. Export the following environment variables:
    1. export CADENCE_ENABLE_AVSREQ_6614_PHASE_1=1
    2. export CADENCE_ENABLE_AVSREQ_12055_PHASE_1=1
  2. Change to the simulation working directory: cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/xcelium
  3. Execute the following command: sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="-sv\ " USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" TOP_LEVEL_NAME="pcie_ed_tb.pcie_ed_tb" | tee simulation.log
    Note: The command above is a single-line command.

A successful simulation includes the following message: "Simulation stopped due to successful completion!"

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