R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
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Ixiasoft
Visible to Intel only — GUID: kjo1614205370702
Ixiasoft
2.7.1. Running the PIO Design Example
- Navigate to ./software/user/example under the design example directory.
- Compile the design example application:
$ make
- Run the test:
$ sudo ./intel_fpga_pcie_link_test
You can run the Intel® FPGA IP PCIe* link test in manual or automatic mode. Choose from:- In automatic mode, the application automatically selects the device. The test selects the Intel PCIe* device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
- In manual mode, the test queries you for the bus, device, and function number and BAR.
For the Intel® Agilex™ Development Kit, you can determine the BDF by typing the following command:
$ lspci -d 1172:
- Here are sample transcripts for automatic and manual modes:
Automatic mode:
Intel FPGA PCIe Link Test - Automatic Mode Version 2.0 0: Automatically select a device 1: Manually select a device *************************************************** >0 Opened a handle to BAR 0 of a device with BDF 0x3800 *************************************************** 0: Link test - 100 writes and reads 1: Write memory space 2: Read memory space 3: Write configuration space 4: Read configuration space 5: Change BAR for PIO 6: Change device 7: Quit program *************************************************** > 0 Doing 100 writes and 100 reads . . Number of write errors: 0 Number of read errors: 0 Number of DWORD mismatches: 0
Manual mode:
Intel FPGA PCIe Link Test
Version 2.0
0: Automatically select a device
1: Manually select a device
****************************************************
> 1
Enter bus number, in hex:
> 4b
Enter device number, in hex:
> 0
BDF is 0x4b00
B:D.F, in hex, is 4b:0.0
Enter BAR number (-1 for none):
> 0
Opened a handle to BAR 0 of a device with BDF 0x4b00