R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 6/20/2022

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2.7. Running the Design Example

Note: The R-Tile Avalon Streaming Intel FGPA IP for PCIe design example has limited hardware testing support on the 22.2 release of Intel® Quartus® Prime. The instructions below can be used for early testing and for the flow required to run the design example on the Intel® Agilex™ I-Series FPGA Development Kit.

Here are the test operations you can perform on the R-tile Avalon® -ST PCIe design examples:

Table 8.  Test Operations Supported by the R-tile Avalon® -ST PCIe Design Examples in the 21.1 Release
Operations Required BAR Supported by R-tile Avalon® -ST PCIe Design Example
0: Link test - 100 writes and reads 0 Yes
1: Write memory space 0 Yes
2: Read memory space 0 Yes
3: Write configuration space N/A Yes
4: Read configuration space N/A Yes
5: Change BAR N/A Yes
6: Change device N/A Yes
Note: When using the Intel® Agilex™ I-Series FPGA Development Kit, set the PCIe REFCLK Select switch to select the clock from the PCIe Connector. For more details, refer to the Intel® Agilex™ I-Series FPGA Development Kit User Guide.