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2.3. Simulating the Design Example
The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the R-tile Avalon® Streaming IP for PCIe (DUT) as shown in the following figure.
For a more detailed description of the testbench and the modules inside it, refer to Testbench. Also, for more details on the Root Port BFM specifically, refer to the Root Port BFM section.
The following flow diagram shows the steps to simulate the design example:
The following figure shows the link status information for a Gen5 x16 Endpoint simulation:
After a successful simulation, the simulation.log file contains the "successful completion" message as shown in the following figure:
This testbench simulates up to a Gen5 x16 variant.
The simulation reports, "Simulation stopped due to successful completion" if no errors occur.
Steps to Run Simulations
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