AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Document Table of Contents PCI Express* IP core

The Intel® Stratix® 10 Hard IP for PCI Express* IP core is a Gen2x8, with a 256-bit interface and running at 125 MHz.

The following table provides information on the configuration fields of the PCI Express* IP core that the reference design uses that are different from the default settings:
Table 3.   PCI Express* IP Core Configuration
Setting Parameter Value
System Settings Application interface type Avalon-MM with DMA
Hard IP mode Gen2:x8, Interface: 256-bit, 125 MHz
Port type Native endpoint
Avalon-MM Settings Enable control register access (CRA) Avalon-MM slave port Disable
Base Address Registers - BAR2 Type 32-bit non-prefetchable memory
Base Address Registers - BAR4 Type 32-bit non-prefetchable memory
Device Identification Registers Vendor ID 0x00001172
Device ID 0x00005052
Revision ID 0x00000001
Class code 0x00ea0001
Subsystem Vendor ID 0x00001172
Subsystem Device ID 0x00000001
PCI Express/PCI Capabilities - Device Maximum payload size 256 Bytes
PHY Characteristics Requested equalization far-end TX preset Preset 9
Note: Instantiate the PCI Express* IP core as part of a Platform Designer system.