AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

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ID 683531
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices A. Reference Design Files
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Stratix® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Stratix® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Intel® Stratix® 10 Partial Reconfiguration Controller IP Core 1.3.1.3.5. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
A. Reference Design Files

1.4. Compiling the Reference Design

In order to compile the other personas in the design, you must export the static region from the compiled base revision. Then, the implementation revisions that define these personas import the static region. To compile the HPR child personas, you must export the HPR parent region from the compiled HPR parent revision. Then, the implementation revisions that define these child personas import the HPR parent region.
  1. To compile the base revision of the reference design, run the following command from the project directory level: 
    quartus_sh --flow compile s10_pcie_devkit_hpr -c s10_pcie_devkit_hpr
    All the implementation revisions, except the base revision contain the following QDB file partition assignment in their respective .qsf files: 
    set_instance_assignment -name QDB_FILE_PARTITION \
      s10_pcie_devkit_pr_static.qdb -to |
    This assignment imports the .qdb file representing the reference design static region logic into the subsequent PR persona implementation compile. Each implementation revision also contains one or two ENTITY_REBINDING assignment. This assignment links the hierarchy of the static region and the hierarchy of the PR persona. For example, s10_pcie_devkit_hpr_ddr4_access.qsf contains the following entity rebinding assignment: 
    set_instance_assignment -name ENTITY_REBINDING \
      parent_persona_top -to \
      u_top|design_core|pr_region_wrapper|pr_persona_wrapper|u_pr_logic
    For more information, please refer to the Partial Reconfiguration Design Flow section in the Partial Reconfiguration User Guide.
  2. To compile all the non-HPR personas, run the following commands: 
    quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_normal_ddr4_access
quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_normal_basic_arithmetic
quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_normal_basic_dsp
	quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_normal_gol.qsf
  3. To compile the HPR parent persona, run the following command: 
    quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_ddr4_access
  4. To export the .qdb representing the parent region, run the following command: 
    quartus_cdb -r s10_pcie_devkit_hpr -c s10_pcie_devkit_hpr_ddr4_access \
      --export_block pr_partition --snapshot final \
      --file s10_pcie_devkit_hpr_ddr4_access_pr_partition_final.qdb \
      --include_sdc_entity_in_partition
    All the HPR child implementation revisions contain an additional QDB FILE PARTITION assignment: 
    set_instance_assignment -name QDB_FILE_PARTITION \
      output_files/s10_pcie_devkit_hpr_ddr4_access_pr_partition_final.qdb -to \
      u_top|design_core|pr_region_wrapper|pr_persona_wrapper|u_pr_logic
    This assignment imports the .qdb file representing the HPR parent region into the subsequent into the subsequent HPR child region compilation. Because the HPR child revisions comprise of two child regions, they contain two ENTITY REBINDING assignments.
  5. To compile the HPR child personas, run the following commands: 
    quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_basic_arithmetic
quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_basic_dsp
	quartus_sh --flow compile s10_pcie_devkit_hpr \
      -c s10_pcie_devkit_hpr_gol
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