AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Document Table of Contents Global Reset Logic

The PLL generates the main clock for this design. All logic, excluding the pcie ip, pr ip, and ddr4 emif run using this 125 MHz clock. The PCIe* generates the global reset, along with the PLL reset signal. On power up, a countdown timer, tcd2um counts down using the internal 50 MHz oscillator, to a 830 μs delay. Until the timer reaches this delay, the PLL is held in reset, deasserting the locked signal. This action freezes the design, and because the PLL locked signal is ORed with the PCIe* reset, the design also is held in reset. Once the timer reaches 830 μs, the design functions normally, and enters a known state.