AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Document Table of Contents

1.1.3. Floorplanning

The floorplan constraints in your partial reconfiguration design physically partitions the device. This partitioning ensures that the resources available to the PR region are the same for any persona that you implement.

To maximize the fabric amount available for the PR region, the reference design constrains the static region to the smallest possible area. This reference design contains two child PR regions of the parent PR region.

Figure 3. Reference Design Floorplan
Note: The child regions contained within the parent PR region can be of any size. The small sizing of the child PR regions in the above figure is for demonstration purposes only.

For more information about floorplanning, refer to Floorplan the Partial Reconfiguration Design section in Volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.