AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Document Table of Contents

1.6. Extending the Reference Design with Custom Persona

This reference design provides an example template to create your own personas for PR over PCIe* . To extend the reference design with your custom persona:
  1. Navigate to the s10_pcie_devkit_hpr folder:
    cd s10_pcie_devkit_hpr
  2. Create a copy of the pr_logic_impl_template.qsf.template implementation revision file:
    cp pr_logic_impl_template.qsf.template <persona_impl_revision_name>.qsf
  3. Create a folder and copy your persona-specific RTL to this folder:
    mkdir <persona_name>
    cp <custom_persona>.sv <persona_name>/
  4. Your custom top-level entity must match the ports for the custom_persona module, defined in the source/templates/ file. The following example shows interfacing your design with the Avalon-MM interface, controlled over PCIe register file:
    module custom_persona #(
    parameter REG_FILE_IO_SIZE = 8
    input wire clk,
    //active low reset, defined by hardware
    input wire rst_n,
    //Persona identification register, used by host in host program
    output wire [31:0] persona_id,
    //Host control register, used for control signals.
    input wire [31:0] host_cntrl_register,
    // 8 registers for host -> PR logic communication
    input wire [31:0] host_pr [0:REG_FILE_IO_SIZE-1],
    // 8 Registers for PR logic -> host communication
    output wire [31:0] pr_host [0:REG_FILE_IO_SIZE-1]

    Utilize any of the parallel I/O port (PIO) register files for customization. The host_pr register sends the data from the persona to the host machine. The pr_host register sends the data from the host machine to the persona.

  5. In your top-level entity file, specify the persona ID as any 32-bit value:
    assign persona_id  = 32'h0000_aeed;
    Note: The example template uses only 8 bits, but you can specify any value, up to 32 bits.
  6. Set the unused output ports of the pr_host register to 0:
    genvar i;
    //Tying unused output ports to zero.
    for (i = 2; i < REG_FILE_IO_SIZE; i = i + 1) begin
       assign pr_host [i] = 32'b0;
  7. Modify your persona_impl_revision_name.qsf to include the following assignments:
    set_global_assignment -name TOP_LEVEL_ENTITY \
          <custom_persona> s10_pcie_ref_design
    set_global_assignment -name SYSTEMVERILOG_FILE \
    set_global_assignment -name QSYS_FILE \
    set_global_assignment -name IP_FILE \
  8. Update the s10_pcie_devkit_hpr.qpf project file to include your implementation revisions:
    PROJECT_REVISION = "<persona_impl_revision_name>"
  9. Compile the revision.

    For complete information on adding a custom persona to a PR design, refer to Adding a New Persona to the Design section in the Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board application note.