AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Document Table of Contents

1.1.1. Clocking Scheme

The reference design creates a separate Altera IOPLL IP core-generated clock. This clock creation decouples the PR logic clocking from both the PCIe* clocking domain that runs at 125 MHz, and the EMIF clocking domain that runs at 233 MHz. The clock for PR Logic is set at 125 MHz. To ensure timing closure, modify the parameterization of the IOPLL IP core to a lower clock frequency.
Figure 2. Timing Closure