AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Document Table of Contents

1.1. Reference Design Overview

The reference design consists of the following components:

  • s10_pcie_reference_design—top-level wrapper for the reference design, connecting the board support package (BSP) subsystem to the device pins.
  • bsp_top—top-level of the design that contains all subsystems of the design. This module consists of three main sub-components - the PCIe* IP core, the DDR4 External Memory Interfaces IP core, and the design top module. This layer of abstraction allows simulation of the design top module through simulated Avalon-MM transactions.
  • design_core—core of the design that handles generation of the PR region, the interface components such as clock crossing Avalon-MM logic and pipeline logic, clocks, and the global reset.
Figure 1.  Intel® Stratix® 10 PCIe* Reference Design Block Diagram