JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

ID 683530
Date 10/14/2022
Document Table of Contents

4. Detailed Description for the JESD204B Design Example

The JESD204B design example demonstrates the functionality of data streaming using loopback mode.

You can specify the parameters settings of your choice and generate the design example.

The design example is available only in duplex mode for both Base and PHY variant. You can choose Base only or PHY only variant but the IP would generate the design example for both Base and PHY.