JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

ID 683530
Date 10/14/2022
Document Table of Contents

4.4. Design Example Clock and Reset

The main reference clocks for the design example are refclk_core and refclk_xcvr. These clocks must be supplied from a single external source (i.e refclk_core and refclk_xcvr must be synchronous to one another). The refclk_core is the reference clock for the core PLL and the refclk_xcvr is the reference clock for the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from refclk_core.

The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon-MM interfaces of Platform Designer components.

Table 16.  Design Example Clocks
Clock Description Source Modules Clocked
refclk_core Reference clock for core PLL External Core PLL
refclk_xcvr Reference clock for TX PLL and RX transceiver PHY External TX PLL and RX transceiver PHY
link_clk Link layer clock refclk_core JESD204B IP core link layer, transport layer link interface
frame_clk Frame layer clock refclk_core Transport layer, test pattern generator and checker, downstream modules
mgmt_clk Control plane clock External Avalon® -MM interfaces
Table 17.  Design Example Resets
Signal Direction Description
global_rst_n Input Global reset to reset entire controller.

For all blocks, except JTAG to Avalon-MM.

mgmt_rst_in_n Internal Reset for Avalon-MM configuration access.
ninit_done Internal Reset for JTAG to Avalon Master bridge component from the Reset Release IP.