JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

ID 683530
Date 10/14/2022
Document Table of Contents

4.7.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

Refer to the instructions in Generating the Design.

Note: Running the hardware test with the design generated as-is is only possible when the JESD204B IP core is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 20.   Intel® Agilex™ Development Kit Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for all supported target development kits.
Port Name Port Description Board Component Component Description
global_rst_n Global reset


User PB0 push-button
refclk_xcvr Transceiver reference clock input


Si549 clock generator
refclk_core Core PLL reference clock input


Si549 clock generator
mgmt_clk Control clock


Si5338 clock generator (CLK1)
tx_serial_data TX serial data


rx_serial_data RX serial data