JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

ID 683530
Date 10/14/2022
Document Table of Contents

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.

To simulate the design, perform the following steps:

  1. Change the working directory to <example_design_directory>/ed_sim/testbench/<Simulator>.
  2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
    Simulator Command
    ModelSim* vsim -do run_tb_top.tcl
    VCS* sh
    VCS* MX sh
    Xcelium* Parallel sh
    The simulation ends with messages that indicate whether the run was successful or not.