1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
|Intel® Quartus® Prime Design Suite 21.3|
|IP Version 19.2.0|
This user guide provides the features, usage guidelines, and detailed description about the design examples for the JESD204B Intel® FPGA IP using Intel® Agilex™ devices.
This document is intended for:
- Design architect to make IP selection during system level design planning phase
- Hardware designers when integrating the IP into their system level design
- Validation engineers during system level simulation and hardware validation phase
|JESD204B Intel® FPGA IP User Guide||This document provides information about the JESD204B Intel® FPGA IP.|
|JESD204B Intel® FPGA IP Release Notes||This document provides release information for the JESD204B Intel® FPGA IP.|
|Intel® Agilex™ Device Data Sheet||
This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.
Acronyms and Glossary
|LMFC||Local Multiframe Clock|
|FC||Frame clock rate|
|ADC||Analog to Digital Converter|
|DAC||Digital to Analog Converter|
|DSP||Digital Signal Processor|
|DLL||Data link layer|
|CSR||Control and status register|
|CRU||Clock and Reset Unit|
|ISR||Interrupt Service Routine|
|ECC||Error Correcting Code|
|SERR||Single Error Detection (in ECC, correctable)|
|DERR||Double Error Detection (in ECC, fatal)|
|PRBS||Pseudorandom binary sequence|
|MAC||Media Access Controller. MAC includes protocol sublayer, transport layer, and data link layer.|
|PHY||Physical Layer. PHY typically includes the physical layer, SERDES, drivers, receivers and CDR.|
|PCS||Physical Coding Sub-layer|
|PMA||Physical Medium Attachment|
|RBD||RX Buffer Delay|
|UI||Unit Interval = duration of serial bit|
|RBD count||RX Buffer Delay latest lane arrival|
|RBD offset||RX Buffer Delay release opportunity|
|Converter Device||ADC or DAC converter|
|Logic Device||FPGA or ASIC|
|Octet||A group of 8 bits, serving as input to 8B/10B encoder and output from the decoder|
Effective data rate per lane for serial link
Data Rate = Sampling rate per converter x M x N' x (10/8)/L
Note: Sampling rate in Msps (Mega samples per second); Data rate in Mbps (Megabits per second)
The associated parallel data bus is 40 bits wide.
Link Clock = Data Rate/40.
|Frame||A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal.|
|Frame Clock||A system clock which runs at the frame's rate.|
|Samples per frame clock||
Samples per clock, the total samples in frame clock for the converter device.
Local multiframe clock is counter generated from the link clock and depends on the F and K parameters.
LMFC Period = (FxK/4) x Link Clock Period; the value of FxK must be divisible by 4.
|Subclass 0||No support for deterministic latency. Data should be immediately released upon lane to lane deskew on receiver.|
|Subclass 1||Deterministic latency using SYSREF.|
|Multipoint Link||Inter-device links with 2 or more converter devices.|
|L||Number of lanes per converter device|
|M||Number of converters per device|
|F||Number of octets per frame on a single lane|
|S||Number of samples transmitted per single converter per frame cycle|
|N’||Total number of bits per sample in the user data format|
|CS||Number of control bits per conversion sample|
|CF||Number of control words per frame clock period per link|
|HD||High Density user data format|
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