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1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Compiling and Testing the Design
4. Detailed Description for the JESD204B Design Example
5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives
6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
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4.6. JESD204B Design Example Status and Control Registers
The JESD204B design example registers use byte-addressing (32 bits).
Refer to the JESD204B Registers section in the JESD204B Intel® FPGA IP User Guide.
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