JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683530
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 2. JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Compiling and Testing the Design 4. Detailed Description for the JESD204B Design Example 5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives 6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Compiling and Simulating the Design x
2.4.1. Testbench
4. Detailed Description for the JESD204B Design Example x
4.1. Presets 4.2. Supported Configurations 4.3. System Components 4.4. Design Example Clock and Reset 4.5. Design Example Signals 4.6. JESD204B Design Example Status and Control Registers 4.7. Hardware Test for System Console Control Design Example
4.3. System Components x
4.3.1. JESD204B Subsystem in Platform Designer 4.3.2. Parallel I/O 4.3.3. Core PLL 4.3.4. SPI Master 4.3.5. Transport Layer 4.3.6. Test Pattern Generator 4.3.7. Test Pattern Checker
4.7. Hardware Test for System Console Control Design Example x
4.7.1. Board Connectivity
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Compiling and Testing the Design
4. Detailed Description for the JESD204B Design Example
5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives
6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

4.4. Design Example Clock and Reset

The main reference clocks for the design example are refclk_core and refclk_xcvr. These clocks must be supplied from a single external source (i.e refclk_core and refclk_xcvr must be synchronous to one another). The refclk_core is the reference clock for the core PLL and the refclk_xcvr is the reference clock for the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from refclk_core.

The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon-MM interfaces of Platform Designer components.

Table 16.  Design Example Clocks
Clock Description Source Modules Clocked
refclk_core Reference clock for core PLL External Core PLL
refclk_xcvr Reference clock for TX PLL and RX transceiver PHY External TX PLL and RX transceiver PHY
link_clk Link layer clock refclk_core JESD204B IP core link layer, transport layer link interface
frame_clk Frame layer clock refclk_core Transport layer, test pattern generator and checker, downstream modules
mgmt_clk Control plane clock External Avalon® -MM interfaces
Table 17.  Design Example Resets
Signal Direction Description
global_rst_n Input Global reset to reset entire controller.

For all blocks, except JTAG to Avalon-MM.

mgmt_rst_in_n Internal Reset for Avalon-MM configuration access.
ninit_done Internal Reset for JTAG to Avalon Master bridge component from the Reset Release IP.
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