Intel® Quartus® Prime Standard Edition User Guide: Programmer

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ID 683528
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Programming Intel FPGA Devices A. Intel® Quartus® Prime Standard Edition User Guides
1. Programming Intel FPGA Devices x
1.1. Programming Flow 1.2. Intel® Quartus® Prime Programmer Window 1.3. Programming and Configuration Modes 1.4. Design Security Keys 1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files 1.6. Convert Programming Files Dialog Box 1.7. Flash Loaders 1.8. JTAG Debug Mode for Partial Reconfiguration 1.9. Scripting Support 1.10. Programming Intel® FPGA Devices Revision History
1.1. Programming Flow x
1.1.1. Stand-Alone Intel® Quartus® Prime Programmer 1.1.2. Optional Programming or Configuration Files 1.1.3. Secondary Programming Files
1.2. Intel® Quartus® Prime Programmer Window x
1.2.1. Editing the Details of an Unknown Device 1.2.2. Setting Up the Hardware 1.2.3. Setting the JTAG Hardware 1.2.4. Using the JTAG Chain Debugger Tool
1.2.3. Setting the JTAG Hardware x
1.2.3.1. Running JTAG Daemon with Linux
1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files x
1.5.1. Obtaining Project Hash for Arria® V, Stratix® V, Cyclone® V and Intel® MAX® 10 Devices 1.5.2. Obtaining Project Hash for Intel® Arria® 10 Devices
1.6. Convert Programming Files Dialog Box x
1.6.1. Debugging Your Configuration 1.6.2. Converting Programming Files for Partial Reconfiguration
1.6.2. Converting Programming Files for Partial Reconfiguration x
1.6.2.1. Generating .pmsf using a .msf and a .sof 1.6.2.2. Generating a .rbf for Partial Reconfiguration from a .pmsf file 1.6.2.3. Enable Decompression During Partial Reconfiguration Option
1.8. JTAG Debug Mode for Partial Reconfiguration x
1.8.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1.9. Scripting Support x
1.9.1. The jtagconfig Debugging Tool 1.9.2. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File 1.9.3. Generating Raw Binary File for Partial Reconfiguration using a .pmsf
1. Programming Intel FPGA Devices
A. Intel® Quartus® Prime Standard Edition User Guides

1.5. Convert Programming Files Tool

The Intel® Quartus® Prime software provides the Convert Programming Files tool (File > Convert Programming Files), which allows you to convert programming files from one file format to another.

The Convert Programming Files tool supports the following design families:

Table 4.  Device Families that the Convert Programming Files Tool Supports
Software Version Supported Device Families
Intel® Quartus® Prime Standard Edition 18.1
  • Intel® Arria® 10
  • Intel® MAX® 10
  • Intel® Cyclone® 10 LP
  • MAX® V
  • Cyclone® V, Arria® V, Stratix® V.

The Convert Programming Files tool also allows you to configure multiple devices with an external host, such as a microprocessor or CPLD. For example, you can combine multiple .sof files into one .pof file.

To save time in subsequent conversions, click Save Conversion Setup to write the conversion specifications in a Conversion Setup File (.cof).

To load a .cof setup in the Convert Programming Files dialog box, click Open Conversion Setup Data .

Conversion Setup File Contents

For example, to store the FPGA data in configuration devices, you can convert the .sof data to another format, such as .pof, .hexout, .rbf, .rpd, or .jic, and then program the configuration device. 

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
	<output_filenameoutput_file.pof</output_filename>
	<n_pages>1</n_pages>
	<width>1</width>
	<mode>14</mode>
	<sof_data>
		<user_name>Page_0</user_name>
		<page_flags>1</page_flags>
		<bit0>
			<sof_filename>/users/user1/template/output_files/template_test.sof</sof_filename> 
		</bit0>
	</sof_data>
	<version>7</version>
	<create_cvp_file>0</create_cvp_file>
	<create_hps_iocsr>0</create_hps_iocsr>
	<auto_create_rpd>0</auto_create_rpd>
	<options>
		<map_file>1</map_file>
	</options>
	<MAX10_device_options>
		<por>0</por>
		<io_pullup>1</io_pullup>
		<auto_reconfigure>1</auto_reconfigure>
		<isp_source>0</isp_source>
		<verify_protect>0</verify_protect>
		<epof>0</epof>
		<ufm_source>0</ufm_source>
	</MAX10_device_options>
	<advanced_options>
		<ignore_epcs_id_check>0</ignore_epcs_id_check>
		<ignore_condone_check>2</ignore_condone_check>
		<plc_adjustment>0</plc_adjustment>
		<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
		<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
		<bitslice_pre_padding>1</bitslice_pre_padding>
	</advanced_options>
</cof>
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