Arria® 10 GX FPGA Development Kit User Guide

Download PDF
ID 683526
Date 11/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 GX FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Development Kit Components 7. Document Revision History for the Arria® 10 GX FPGA Development Kit User Guide A. Safety and Regulatory Compliance Information
1. Arria® 10 GX FPGA Development Kit Overview x
1.1. Block Diagram 1.2. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The Sys Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIE Tab 4.4.7. The FMCA Tab 4.4.8. The FMCB Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Development Kit Components x
6.1. Board Overview 6.2. MAX® V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughter Cards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. Onboard Oscillators 6.6.2. Offboard Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express* 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughter Cards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Arria® 10 GX FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Development Kit Components
7. Document Revision History for the Arria® 10 GX FPGA Development Kit User Guide
A. Safety and Regulatory Compliance Information

6.5.2. User-Defined DIP Switch

The Arria® 10 GX FPGA development board includes a set of eight-pin DIP switch. There are no board-specific functions for these switches. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected.

Table 30.  User-Defined DIP Switch Schematic Signal Names and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard

1

USER_DIPSW0

A24

1.8 V

2

USER_DIPSW1

B23

1.8 V

3

USER_DIPSW2

A23

1.8 V

4

USER_DIPSW3

B22

1.8 V

5

USER_DIPSW4

A22

1.8 V

6

USER_DIPSW5

B21

1.8 V

7

USER_DIPSW6

C21

1.8 V

8

USER_DIPSW7

A20

1.8 V
Level Two Title