Arria® 10 GX FPGA Development Kit User Guide

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ID 683526
Date 11/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 GX FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Development Kit Components 7. Document Revision History for the Arria® 10 GX FPGA Development Kit User Guide A. Safety and Regulatory Compliance Information
1. Arria® 10 GX FPGA Development Kit Overview x
1.1. Block Diagram 1.2. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The Sys Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIE Tab 4.4.7. The FMCA Tab 4.4.8. The FMCB Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Development Kit Components x
6.1. Board Overview 6.2. MAX® V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughter Cards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. Onboard Oscillators 6.6.2. Offboard Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express* 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughter Cards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Arria® 10 GX FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Development Kit Components
7. Document Revision History for the Arria® 10 GX FPGA Development Kit User Guide
A. Safety and Regulatory Compliance Information

6.10.1.5. FMC Loopback Card

The Arria® 10 GX FPGA Development Kit provides two FMC mezzanine interface ports connected to the Arria® 10 GX FPGA for interfacing to Altera® FMC add-in boards as shown in the figure below. The Altera FMC interface is mechanically compliant with the Vita 57.1 specification for attaching a double width mezzanine module. However, in terms of signal connections, the Altera FMC interface is not fully compliant with the Vita 57.1 specification. Instead, it contains a subset of the Vita 57.1 interface signal to the connector as shown in the FMCA and FMCB signal assignments tables.

Figure 46.  Arria® 10 GX FPGA Development Kit FMC Block Diagram

The following shows the complete signal connections assigned for each Altera FMC interface at the FMCA port (J1) and FMCB port (J2). For the signal connections to the FPGA device, refer to the FMC section.

Table 56.  FMCA Connector (J1) Signal Assignments
K J H G F E D C B A
1 NC GND VREF_FMCA GND FMCA_M2C_PG GND FMCA_C2M_PG GND NC GND
2 GND NC FMCA_PRSNTn FMCA_CLK_M2C_P1 GND NC GND FMCA_DP_C2M_P0 GND FMCA_DP_M2C_P1
3 GND NC GND FMCA_CLK_M2C_N1 GND NC GND FMCA_DP_C2M_N0 GND FMCA_DP_M2C_N1
4 FMCA_DP_M2C_P10 GND FMCA_CLK_M2C_P0 GND NC GND FMCA_GBTCLK_M2C_P0 GND FMCA_DP_M2C_P9 GND
5 FMCA_DP_M2C_N10 GND FMCA_CLK_M2C_N0 GND NC GND FMCA_GBTCLK_M2C_N0 GND FMCA_DP_M2C_N9 GND
6 GND NC GND FMCA_LA_RX_CLK_P0 GND NC GND FMCA_DP_M2C_P0 GND FMCA_DP_M2C_P2
7 FMCA_DP_M2C_P11 GND FMCA_LA_TX_P0 FMCA_LA_RX_CLK_N0 NC NC GND FMCA_DP_M2C_N0 GND FMCA_DP_M2C_N2
8 FMCA_DP_M2C_N11 GND FMCA_LA_TX_N0 GND NC GND FMCA_LA_RX_CLK_P1 GND FMCA_DP_M2C_P8 GND
9 GND NC GND FMCA_LA_RX_P0 GND NC FMCA_LA_RX_CLK_N1 GND FMCA_DP_M2C_N8 GND
10 FMCA_DP_M2C_P12 GND FMCA_LA_TX_P1 FMCA_LA_RX_N0 NC NC GND FMCA_LA_RX_P1 GND FMCA_DP_M2C_P3
11 FMCA_DP_M2C_N12 GND FMCA_LA_TX_N1 GND NC GND FMCA_LA_TX_P2 FMCA_LA_RX_N1 GND FMCA_DP_M2C_N3
12 GND NC GND FMCA_LA_RX_P2 GND NC FMCA_LA_TX_N2 GND FMCA_DP_M2C_P7 GND
13 FMCA_DP_M2C_P13 GND FMCA_LA_TX_P3 FMCA_LA_RX_N2 NC NC GND GND FMCA_DP_M2C_N7 GND
14 FMCA_DP_M2C_N13 GND FMCA_LA_TX_N3 GND NC GND FMCA_LA_TX_P4 FMCA_LA_RX_P3 GND FMCA_DP_M2C_P4
15 GND NC GND FMCA_LA_RX_P4 GND NC FMCA_LA_TX_N4 FMCA_LA_RX_N3 GND FMCA_DP_M2C_N4
16 FMCA_DP_M2C_P14 GND FMCA_LA_TX_P5 FMCA_LA_RX_N4 NC NC GND GND FMCA_DP_M2C_P6 GND
17 FMCA_DP_M2C_N14 GND FMCA_LA_TX_N5 GND NC GND FMCA_LA_TX_P6 GND FMCA_DP_M2C_N6 GND
18 GND NC GND FMCA_LA_RX_P6 GND NC FMCA_LA_TX_N6 FMCA_LA_RX_P5 GND FMCA_DP_M2C_P5
19 FMCA_DP_M2C_P15 GND FMCA_LA_TX_P7 FMCA_LA_RX_N6 NC NC GND FMCA_LA_RX_N5 GND FMCA_DP_M2C_N5
20 FMCA_DP_M2C_N15 GND FMCA_LA_TX_N7 GND NC GND FMCA_LA_TX_P8 GND FMCA_GBTCLK_M2C_P1 GND
21 GND NC GND FMCA_LA_RX_P8 GND NC FMCA_LA_TX_N8 GND FMCA_GBTCLK_M2C_N1 GND
22 FMCA_DP_C2M_P10 GND FMCA_LA_TX_P9 FMCA_LA_RX_N8 NC NC GND FMCA_LA_RX_P7 GND FMCA_DP_C2M_P1
23 FMCA_DP_C2M_N10 GND FMCA_LA_TX_N9 GND NC GND FMCA_LA_TX_P11 FMCA_LA_RX_N7 GND FMCA_DP_C2M_N1
24 GND NC GND FMCA_LA_RX_P9 GND NC FMCA_LA_TX_N11 GND FMCA_DP_C2M_P9 GND
25 FMCA_DP_C2M_P11 GND FMCA_LA_TX_P10 FMCA_LA_RX_N9 NC NC GND GND FMCA_DP_C2M_N9 GND
26 FMCA_DP_C2M_N11 GND FMCA_LA_TX_N10 GND NC GND FMCA_LA_TX_P13 FMCA_LA_RX_P11 GND FMCA_DP_C2M_P2
27 GND NC GND FMCA_LA_RX_P10 GND NC FMCA_LA_TX_N13 FMCA_LA_RX_N11 GND FMCA_DP_C2M_N2
28 FMCA_DP_C2M_P12 GND FMCA_LA_TX_P12 FMCA_LA_RX_N10 NC NC GND GND FMCA_DP_C2M_P8 GND
29 FMCA_DP_C2M_N12 GND FMCA_LA_TX_N12 GND NC GND FMCA_JTAG_TCK GND FMCA_DP_C2M_N8 GND
30 GND NC GND FMCA_LA_RX_P12 GND NC FMCA_JTAG_TDI FMCA_3P3V_SCL GND FMCA_DP_C2M_P3
31 FMCA_DP_C2M_P13 GND FMCA_LA_TX_P14 FMCA_LA_RX_N12 NC NC FMCA_JTAG_TDO FMCA_3P3V_SDA GND FMCA_DP_C2M_N3
32 FMCA_DP_C2M_N13 GND FMCA_LA_TX_N14 GND NC GND 3.3V GND FMCA_DP_C2M_P7 GND
33 GND NC GND FMCA_LA_RX_P13 GND NC FMCA_JTAG_TMS GND FMCA_DP_C2M_N7 GND
34 FMCA_DP_C2M_P14 GND FMCA_LA_TX_P15 FMCA_LA_RX_N13 NC NC FMCA_JTAG_RST FMCA_GA0 GND FMCA_DP_C2M_P4
35 FMCA_DP_C2M_N14 GND FMCA_LA_TX_N15 GND NC GND FMCA_GA1 12V GND FMCA_DP_C2M_N4
36 GND NC GND FMCA_LA_RX_P14 GND NC 3.3V GND FMCA_DP_C2M_P6 GND
37 FMCA_DP_C2M_P15 GND FMCA_LA_TX_P16 FMCA_LA_RX_N14 NC NC GND 12V FMCA_DP_C2M_N6 GND
38 FMCA_DP_C2M_N15 GND FMCA_LA_TX_N16 GND NC GND 3.3V GND GND FMCA_DP_C2M_P5
39 GND NC GND A10_VCCIO_FMCA GND A10_VCCIO_FMCA GND 3.3V GND FMCA_DP_C2M_N5
40 NC GND A10_VCCIO_FMCA GND A10_VCCIO_FMCA GND 3.3V GND NC GND
LPC Connector LPC Connector HPC Connector HPC Connector
Table 57.  FMCB Connector (J2) Signals Assignments
K J H G F E D C B A
1 NC GND VREF_FMCB GND FMCB_M2C_PG GND FMCB_C2M_PG GND NC GND
2 GND NC FMCB_PRSNTn FMCB_CLK_M2C_P1 GND NC GND FMCB_DP_C2M_P0 GND FMCB_DP_M2C_P1
3 GND NC GND FMCB_CLK_M2C_N1 GND NC GND FMCB_DP_C2M_N0 GND FMCB_DP_M2C_N1
4 FMCB_DP_M2C_P10 GND FMCB_CLK_M2C_P0 GND NC GND FMCB_GBTCLK_M2C_P0 GND FMCB_DP_M2C_P9 GND
5 FMCB_DP_M2C_N10 GND FMCB_CLK_M2C_N0 GND NC GND FMCB_GBTCLK_M2C_N0 GND FMCB_DP_M2C_N9 GND
6 GND NC GND FMCB_LA_RX_CLK_P0 GND NC GND FMCB_DP_M2C_P0 GND FMCB_DP_M2C_P2
7 FMCB_DP_M2C_P11 GND FMCB_LA_TX_P0 FMCB_LA_RX_CLK_N0 NC NC GND FMCB_DP_M2C_N0 GND FMCB_DP_M2C_N2
8 FMCB_DP_M2C_N11 GND FMCB_LA_TX_N0 GND NC GND FMCB_LA_RX_CLK_P1 GND FMCB_DP_M2C_P8 GND
9 GND NC GND FMCB_LA_RX_P0 GND NC FMCB_LA_RX_CLK_N1 GND FMCB_DP_M2C_N8 GND
10 FMCB_DP_M2C_P12 GND FMCB_LA_TX_P1 FMCB_LA_RX_N0 NC NC GND FMCB_LA_RX_P1 GND FMCB_DP_M2C_P3
11 FMCB_DP_M2C_N12 GND FMCB_LA_TX_N1 GND NC GND FMCB_LA_TX_P2 FMCB_LA_RX_N1 GND FMCB_DP_M2C_N3
12 GND NC GND FMCB_LA_RX_P2 GND NC FMCB_LA_TX_N2 GND FMCB_DP_M2C_P7 GND
13 FMCB_DP_M2C_P13 GND FMCB_LA_TX_P3 FMCB_LA_RX_N2 NC NC GND GND FMCB_DP_M2C_N7 GND
14 FMCB_DP_M2C_N13 GND FMCB_LA_TX_N3 GND NC GND FMCB_LA_TX_P4 FMCB_LA_RX_P3 GND FMCB_DP_M2C_P4
15 GND NC GND FMCB_LA_RX_P4 GND NC FMCB_LA_TX_N4 FMCB_LA_RX_N3 GND FMCB_DP_M2C_N4
16 FMCB_DP_M2C_P14 GND FMCB_LA_TX_P5 FMCB_LA_RX_N4 NC NC GND GND FMCB_DP_M2C_P6 GND
17 FMCB_DP_M2C_N14 GND FMCB_LA_TX_N5 GND NC GND FMCB_LA_TX_P6 GND FMCB_DP_M2C_N6 GND
18 GND NC GND FMCB_LA_RX_P6 GND NC FMCB_LA_TX_N6 FMCB_LA_RX_P5 GND FMCB_DP_M2C_P5
19 FMCB_DP_M2C_P15 GND FMCB_LA_TX_P7 FMCB_LA_RX_N6 NC NC GND FMCB_LA_RX_N5 GND FMCB_DP_M2C_N5
20 FMCB_DP_M2C_N15 GND FMCB_LA_TX_N7 GND NC GND FMCB_LA_TX_P8 GND FMCB_GBTCLK_M2C_P1 GND
21 GND NC GND FMCB_LA_RX_P8 GND NC FMCB_LA_TX_N8 GND FMCB_GBTCLK_M2C_N1 GND
22 FMCB_DP_C2M_P10 GND FMCB_LA_TX_P9 FMCB_LA_RX_N8 NC NC GND FMCB_LA_RX_P7 GND FMCB_DP_C2M_P1
23 FMCB_DP_C2M_N10 GND FMCB_LA_TX_N9 GND NC GND FMCB_LA_TX_P11 FMCB_LA_RX_N7 GND FMCB_DP_C2M_N1
24 GND NC GND FMCB_LA_RX_P9 GND NC FMCB_LA_TX_N11 GND FMCB_DP_C2M_P9 GND
25 FMCB_DP_C2M_P11 GND FMCB_LA_TX_P10 FMCB_LA_RX_N9 NC NC GND GND FMCB_DP_C2M_N9 GND
26 FMCB_DP_C2M_N11 GND FMCB_LA_TX_N10 GND NC GND FMCB_LA_TX_P13 FMCB_LA_RX_P11 GND FMCB_DP_C2M_P2
27 GND NC GND FMCB_LA_RX_P10 GND NC FMCB_LA_TX_N13 FMCB_LA_RX_N11 GND FMCB_DP_C2M_N2
28 FMCB_DP_C2M_P12 GND FMCB_LA_TX_P12 FMCB_LA_RX_N10 NC NC GND GND FMCB_DP_C2M_P8 GND
29 FMCB_DP_C2M_N12 GND FMCB_LA_TX_N12 GND NC GND FMCB_JTAG_TCK GND FMCB_DP_C2M_N8 GND
30 GND NC GND FMCB_LA_RX_P12 GND NC FMCB_JTAG_TDI FMCB_3P3V_SCL GND FMCB_DP_C2M_P3
31 FMCB_DP_C2M_P13 GND FMCB_LA_TX_P14 FMCB_LA_RX_N12 NC NC FMCB_JTAG_TDO FMCB_3P3V_SDA GND FMCB_DP_C2M_N3
32 FMCB_DP_C2M_N13 GND FMCB_LA_TX_N14 GND NC GND 3.3V GND FMCB_DP_C2M_P7 GND
33 GND NC GND FMCB_LA_RX_P13 GND NC FMCB_JTAG_TMS GND FMCB_DP_C2M_N7 GND
34 FMCB_DP_C2M_P14 GND FMCB_LA_TX_P15 FMCB_LA_RX_N13 NC NC FMCB_JTAG_RST FMCB_GA0 GND FMCB_DP_C2M_P4
35 FMCB_DP_C2M_N14 GND FMCB_LA_TX_N15 GND NC GND FMCB_GA1 12V GND FMCB_DP_C2M_N4
36 GND NC GND FMCB_LA_RX_P14 GND NC 3.3V GND FMCB_DP_C2M_P6 GND
37 FMCB_DP_C2M_P15 GND FMCB_LA_TX_P16 FMCB_LA_RX_N14 NC NC GND 12V FMCB_DP_C2M_N6 GND
38 FMCB_DP_C2M_N15 GND FMCB_LA_TX_N16 GND NC GND 3.3V GND GND FMCB_DP_C2M_P5
39 GND NC GND A10_VCCIO_FMCB GND A10_VCCIO_FMCB GND 3.3V GND FMCB_DP_C2M_N5
40 NC GND A10_VCCIO_FMCB GND A10_VCCIO_FMCB GND 3.3V GND NC GND
LPC Connector LPC Connector HPC Connector HPC Connector

Section Content
High Pin Count (HBC)
Low Pin Count (LPC)

Level Two Title