Intel® Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 1/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Intel® Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the USB-Blaster Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Intel® Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.7.7. I2C

I2C supports communication between integrated circuits on a board. It is a simple two-wire bus that consists of a serial data line (SDA) and a serial clock (SCL). The MAX V and Intel® Arria® 10 devices use the I2C for reading and writing to the character LCD. You can use the Intel® Arria® 10 or MAX V as the I2C host to access the PLLs and clocks.

Figure 34. I2C Block Diagram
Table 37.  MAX V I2C Signals
Schematic Signal Name Pin Number I/O Standard Description
CLOCK_I2C_SCL C12 2.5 V I2C serial clock from MAX V.
CLOCK_I2C_SDA C10 2.5 V I2C serial data from MAX V.
Table 38.  MAX V I2C Level Shifter Signals to Intel® Arria® 10 FPGA
Schematic Signal Name Intel® Arria® 10 Pin Number I/O Standard Description
CLOCK_SCL AN30 1.8 V Intel® Arria® 10 FPGA I2C serial clock from MAX V level shifter.
CLOCK_SDA AV33 1.8 V Intel® Arria® 10 FPGA I2C serial data from MAX V level shifter.
Table 39.   Intel® Arria® 10 I2C Signals
Schematic Signal Name Pin Number I/O Standard Description
DISP_I2C_SCL AW33 1.8 V Intel® Arria® 10 I2C serial clock to level shifter.
DISP_I2C_SDA AY34 1.8 V Intel® Arria® 10 I2C serial data to level shifter.
Table 40.   Intel® Arria® 10 I2C Level Shifter to LCD Signals
Schematic Signal Name LCD Pin Number I/O Standard Description
I2C_SCL_DISP 7 5.0 V LCD I2C serial clock from Intel® Arria® 10 FPGA level shifter.
I2C_SDA_DISP 8 5.0 V LCD I2C serial data from Intel® Arria® 10 FPGA level shifter.
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