Intel® Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 1/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Intel® Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the USB-Blaster Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Intel® Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

3.2. Default Switch and Jumper Settings

This topic shows you how to restore the default factory settings and explains their functions.
CAUTION:
Do not install or remove jumpers (shunts) while the development board is powered on.
Figure 5. Default Switch and Jumper Settings on the Top
Figure 6. Default Switch Settings on the Bottom
  1. Set DIP switch bank (SW3) to match the following table.
    Table 2.  SW3 DIP PCIe Switch Default Settings (Board Top)
    Switch Board Label Function Default Position
    1 x1 ON for PCIe x1 ON
    2 x4 ON for PCIe x4 ON
    3 x8 ON for PCIe x8 ON
    4 — OFF for 1.35 V MEM_VDD power rail OFF

  2. If all of the jumper blocks are open, the FMCA and FMCB VCCIO value is 1.2 V. To change that value, add shunts as shown in the following table.
    Table 3.  Default Jumper Settings for the FPGA Mezzanine Card (FMC) Ports (Board Top)
    Board Reference Board Label Description
    J8 pins 1-2 1.35V 1.35 V FMCB VCCIO select
    J8 pins 3-4 1.5V 1.5 V FMCB VCCIO select
    J8 pins 5-6 1.8V 1.8 V FMCB VCCIO select
    J11 pins 1-2 1.35V 1.35 V FMCA VCCIO select
    J11 pins 3-4 1.5V 1.5 V FMCA VCCIO select
    J11 pins 5-6 1.8V 1.8 V FMCA VCCIO select

  3. Set DIP switch bank (SW4) to match the following table.
    Table 4.  SW4 JTAG DIP Switch Default Settings (Board Bottom)
    Switch Board Label Function Default Position
    1 Intel® Arria® 10 OFF to enable the Intel® Arria® 10 in the JTAG chain OFF
    2 MAX V OFF to enable the MAX V in the JTAG chain OFF
    3 FMCA ON to bypass the FMCA connector in the JTAG chain ON
    4 FMCB ON to bypass the FMCB connector in the JTAG chain ON

  4. Set DIP switch bank (SW5) to match the following table.
    Table 5.  SW5 DIP Switch Default Settings (Board Bottom)
    Switch Board Label Function Default Position
    1 MSEL0 OFF for MSEL0 = 1; for FPP standard mode OFF
    2 MSEL1 ON for MSEL1 = 0; for FPP standard mode ON
    3 MSEL2 ON for MSEL2 = 0; for FPP standard mode ON
    4 VIDEN OFF for enabling VID_EN for the Smart Voltage ID (SmartVID) feature ON

  5. Set DIP switch bank (SW6) to match the following table.
    Table 6.  SW6 DIP Switch Default Settings (Board Bottom)
    Switch Board Label Function Default Position
    1 CLK_SEL ON for 100 MHz on-board clock oscillator selection

    OFF for SMA input clock selection

    		ON
    2 CLK_EN OFF for setting CLK_ENABLE signal high to the MAV V OFF
    3 Si516_FS ON for setting the SDI REFCLK frequency to 148.35 MHz

    OFF for setting the SDI REFCLK frequency to 148.5 MHz

    		OFF
    4 FACTORY ON to load factory image from flash

    OFF to load user image #1 from flash

    		ON
    5 RZQ_B2K ON for setting RZQ resistor of Bank 2K to 99.17 ohm

    OFF for setting RZQ resistor of Bank 2K to 240 ohm

    		OFF
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