Intel® Arria® 10 FPGA Development Kit User Guide

Download PDF
ID 683526
Date 1/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Intel® Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the USB-Blaster Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Intel® Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.2. MAX V CPLD System Controller

The board utilizes the EPM2210 System Controller, a MAX V CPLD, for the following purposes:

  • FPGA configuration from flash memory
  • Power consumption monitoring
  • Temperature monitoring
  • Fan control
  • Control registers for clocks
  • Control registers for remote update system
Table 16.  MAX V CPLD System Controller Device Pin-Out

Schematic Signal Name

Pin Number

I/O Standard Description

CLK125_EN

E9

2.5 V

 125 MHz oscillator enable

CLK50_EN

J16

1.8 V

 50 MHz oscillator enable

CLK_CONFIG

J5

1.8 V

 Clock Configure

CLK_ENABLE

D4

2.5 V

 Clock Enable

CLK_SEL

A2

2.5 V

 Clock Select

CLOCK_I2C_SCL

C12

2.5 V

 Serial clock line for I2C

CLOCK_I2C_SDA

C10

2.5 V

 Serial data line for I2C

CPU_RESETN

K4

1.8 V

 FPGA reset push button

FACTORY_LOAD

B5

2.5 V

 DIP switch to load factory or user design at power-up

FLASH_ADVN

N14

1.8 V

 FSM bus flash memory address valid

FLASH_CEN0

D14

1.8 V

 FSM bus flash memory chip enable

FLASH_CEN1

F11

1.8 V

 FSM bus flash memory chip enable

FLASH_CLK

N15

1.8 V

 FSM bus flash memory clock

FLASH_OEN

P14

1.8 V

 FSM bus flash memory output enable

FLASH_RDYBSYN0

F12

1.8 V

 FSM bus flash memory ready

FLASH_RDYBSYN1

P15

1.8 V

 FSM bus flash memory ready

FLASH_RESETN

D13

1.8 V

 FSM bus flash memory reset

FLASH_WEN

J1

1.8 V

 FSM bus flash memory write enable

FM_A1

F15

1.8 V

 FM address bus

FM_A2

G16

1.8 V

 FM address bus

FM_A3

G15

1.8 V

 FM address bus

FM_A4

H16

1.8 V

 FM address bus

FM_A5

H15

1.8 V

 FM address bus

FM_A6

F16

1.8 V

 FM address bus

FM_A7

G14

1.8 V

 FM address bus

FM_A8

D16

1.8 V

 FM address bus

FM_A9

E15

1.8 V

 FM address bus

FM_A10

E16

1.8 V

 FM address bus

FM_A11

H14

1.8 V

 FM address bus

FM_A12

D15

1.8 V

 FM address bus

FM_A13

F14

1.8 V

 FM address bus

FM_A14

C14

1.8 V

 FM address bus

FM_A15

C15

1.8 V

 FM address bus

FM_A16

H3

1.8 V

 FM address bus

FM_A17

H2

1.8 V

 FM address bus

FM_A18

E13

1.8 V

 FM address bus

FM_A19

F13

1.8 V

 FM address bus

FM_A20

G13

1.8 V

 FM address bus

FM_A21

G12

1.8 V

 FM address bus

FM_A22

E12

1.8 V

 FM address bus

FM_A23

J13

1.8 V

 FM address bus

FM_A24

G5

1.8 V

 FM address bus

FM_A25

H13

1.8 V

 FM address bus

FM_A26

H4

1.8 V

 FM address bus

FM_D0

J15

1.8 V

 FM data bus

FM_D1

L16

1.8 V

 FM data bus

FM_D2

L14

1.8 V

 FM data bus

FM_D3

K14

1.8 V

 FM data bus

FM_D4

L13

1.8 V

 FM data bus

FM_D5

L15

1.8 V

 FM data bus

FM_D6

M15

1.8 V

 FM data bus

FM_D7

M16

1.8 V

 FM data bus

FM_D8

K16

1.8 V

 FM data bus

FM_D9

K15

1.8 V

 FM data bus

FM_D10

J14

1.8 V

 FM data bus

FM_D11

K13

1.8 V

 FM data bus

FM_D12

L12

1.8 V

 FM data bus

FM_D13

N16

1.8 V

 FM data bus

FM_D14

M13

1.8 V

 FM data bus

FM_D15

L11

1.8 V

 FM data bus

FM_D16

E4

1.8 V

 FM data bus

FM_D17

F6

1.8 V

 FM data bus

FM_D18

F4

1.8 V

 FM data bus

FM_D19

C2

1.8 V

 FM data bus

FM_D20

D1

1.8 V

 FM data bus

FM_D21

F1

1.8 V

 FM data bus

FM_D22

E3

1.8 V

 FM data bus

FM_D23

G2

1.8 V

 FM data bus

FM_D24

E5

1.8 V

 FM data bus

FM_D25

C3

1.8 V

 FM data bus

FM_D26

D3

1.8 V

 FM data bus

FM_D27

D2

1.8 V

 FM data bus

FM_D28

E1

1.8 V

 FM data bus

FM_D29

G3

1.8 V

 FM data bus

FM_D30

F3

1.8 V

 FM data bus

FM_D31

F2

1.8 V

 FM data bus

FMCA_C2M_PG

R16

1.8 V

 FMC port A power good output

FMCA_PRSNTN

G1

1.8 V

 Green LED. Illuminates when the FMC port has a board or cable plugged-in. Driven by the add-in card.

FMCB_C2M_PG

L5

1.8 V

 FMC port B power good output

FMCB_PRSNTN

E2

1.8 V

 Green LED. Illuminates when the FMC port has a board or cable plugged-in. Driven by the add-in card.

FPGA_CONF_DONE

K1

1.8 V

 FPGA configuration done LED

FPGA_CONFIG_D0

R1

1.8 V

 FPGA configuration data

FPGA_CONFIG_D1

T2

1.8 V

 FPGA configuration data

FPGA_CONFIG_D2

N6

1.8 V

 FPGA configuration data

FPGA_CONFIG_D3

N5

1.8 V

 FPGA configuration data

FPGA_CONFIG_D4

N7

1.8 V

 FPGA configuration data

FPGA_CONFIG_D5

N8

1.8 V

 FPGA configuration data

FPGA_CONFIG_D6

M12

1.8 V

 FPGA configuration data

FPGA_CONFIG_D7

T13

1.8 V

 FPGA configuration data

FPGA_CONFIG_D8

T15

1.8 V

 FPGA configuration data

FPGA_CONFIG_D9

R13

1.8 V

 FPGA configuration data

FPGA_CONFIG_D10

P4

1.8 V

 FPGA configuration data

FPGA_CONFIG_D11

R3

1.8 V

 FPGA configuration data

FPGA_CONFIG_D12

T10

1.8 V

 FPGA configuration data

FPGA_CONFIG_D13

P5

1.8 V

 FPGA configuration data

FPGA_CONFIG_D14

R4

1.8 V

 FPGA configuration data

FPGA_CONFIG_D15

R5

1.8 V

 FPGA configuration data

FPGA_CONFIG_D16

M8

1.8 V

 FPGA configuration data

FPGA_CONFIG_D17

M7

1.8 V

 FPGA configuration data

FPGA_CONFIG_D18

T5

1.8 V

 FPGA configuration data

FPGA_CONFIG_D19

P9

1.8 V

 FPGA configuration data

FPGA_CONFIG_D20

M6

1.8 V

 FPGA configuration data

FPGA_CONFIG_D21

N9

1.8 V

 FPGA configuration data

FPGA_CONFIG_D22

R8

1.8 V

 FPGA configuration data

FPGA_CONFIG_D23

T8

1.8 V

 FPGA configuration data

FPGA_CONFIG_D24

P7

1.8 V

 FPGA configuration data

FPGA_CONFIG_D25

R7

1.8 V

 FPGA configuration data

FPGA_CONFIG_D26

R9

1.8 V

 FPGA configuration data

FPGA_CONFIG_D27

T9

1.8 V

 FPGA configuration data

FPGA_CONFIG_D28

T7

1.8 V

 FPGA configuration data

FPGA_CONFIG_D29

P8

1.8 V

 FPGA configuration data

FPGA_CONFIG_D30

R6

1.8 V

 FPGA configuration data

FPGA_CONFIG_D31

P6

1.8 V

 FPGA configuration data

FPGA_CVP_CONFDONE

M14

1.8 V

 FPGA Configuration via Protocol (CvP) done

FPGA_DCLK

M9

1.8 V

 FPGA configuration clock

FPGA_NCONFIG

E14

1.8 V

 FPGA configuration active

FPGA_NSTATUS

J4

1.8 V

 FPGA configuration ready

FPGA_PR_DONE

H12

1.8 V

 FPGA partial reconfiguration done

FPGA_PR_ERROR

K12

1.8 V

 FPGA partial reconfiguration error

FPGA_PR_READY

P12

1.8 V

 FPGA partial reconfiguration ready

FPGA_PR_REQUEST

T4

1.8 V

 FPGA partial reconfiguration request

M5_JTAG_TCK

P3

1.8 V

 JTAG chain clock

M5_JTAG_TDI

L6

1.8 V

 JTAG chain data in

M5_JTAG_TDO

M5

1.8 V

 JTAG chain data out

M5_JTAG_TMS

N4

1.8 V

 JTAG chain mode

MAX5_BEN0

R10

1.8 V

 MAX V Byte Enable 0

MAX5_BEN1

M10

1.8 V

 MAX V Byte Enable 1

MAX5_BEN2

T12

1.8 V

 MAX V Byte Enable 2

MAX5_BEN3

P10

1.8 V

 MAX V Byte Enable 3

MAX5_CLK

N11

1.8 V

 MAX V Clock

MAX5_CSN

T11

1.8 V

 MAX V chip select

MAX5_OEN

N10

1.8 V

 MAX V output enable

MAX5_WEN

R11

1.8 V

 MAX V Write enable

MAX_CONF_DONE

D7

2.5 V

 On-board USB-Blaster II configuration done LED

MAX_ERROR

C7

2.5 V

 FPGA configuration error LED

MAX_LOAD

B6

2.5 V

 FPGA configuration active LED

MAX_RESETN

J3

1.8 V

 MAX V reset push button

MSEL0

R12

1.8 V

 FPGA MSEL0 setting

MSEL1

P11

1.8 V

 FPGA MSEL1 setting

MSEL2

M11

1.8 V

 FPGA MSEL2 setting

MV_CLK_50

J12

1.8 V

 MAX V 50 MHz clock

OVERTEMP

E11

2.5 V

 Temperature monitor fan enable

OVERTEMPN

B16

2.5 V

 Temperature monitor fan enable

PGM_CONFIG

A6

2.5 V

 Load the flash memory image identified by the PGM LEDs

PGM_LED0

D6

2.5 V

 Flash memory PGM select indicator 0

PGM_LED1

C6

2.5 V

 Flash memory PGM select indicator 1

PGM_LED2

B7

2.5 V

 Flash memory PGM select indicator 2

PGM_SEL

A7

2.5 V

 Toggles the PGM_LED[2:0] LED sequence

SDI_MF0_BYPASS

P13

1.8 V

 SDI Interface Mode Select 0 / Bypass control

SDI_MF1_AUTO_SLEEP

R14

1.8 V

 SDI Interface Mode Select 1 / Auto Sleep Control

SDI_MF2_MUTE

N12

1.8 V

 SDI Interface Mode Select 2 / Output Mute

SDI_TX_SD_HDN

N13

1.8 V

 SDI Interface TX Signal Detect

SENSE_CS0N

D9

2.5 V

 SPI Interface Chip Select

SENSE_SCK

B9

2.5 V

 SPI Interface Clock

SENSE_SDI

B3

2.5 V

 SPI Interface Serial Data In

SENSE_SDO

C9

2.5 V

 SPI Interface Serial Data Out

SENSE_SMB_CLK

A15

2.5 V

I2C Interface Clock

SENSE_SMB_DATA

B13

2.5 V

 I2C Interface Data

SI516_FS

C5

2.5 V

Silicon Labs SI516 Clock Device Frequency Select

SI570_EN

A10

2.5 V

 Si570 programmable clock enable

TSENSE_ALERTN

B14

2.5 V

 MAX1619 device Temperature Sense Alert Signal

USB_CFG0

M4

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG1

M3

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG2

K2

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG3

K5

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG4

L1

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG5

L2

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG6

K3

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG7

M2

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG8

L4

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG9

L3

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG10

N1

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG11

N2

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG12

M1

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG13

N3

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_CFG14

P2

1.8 V

 On-board USB-Blaster II interface (reserved for future use)

USB_M5_CLK

H5

1.8 V

 On-board USB-Blaster II interface clock

ED8101_ALERT

B8

2.5 V

 ED8101 Alert signal

ED8101_SCL

A8

2.5 V

 ED8101 I2C clock signal

ED8101_SDA

A9

2.5 V

 ED8101 I2C data signal
Level Two Title