Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 1/19/2024
Document Table of Contents

3.1. Design Example Directory Structure

Table 33.  Directory Structure
Directory / File Sub-directory / File Sub-directory / File Sub-directory / File Sub-directory / File Note
pcie_ed sim pcie_ed.v Design example top-level HDL
<simulators> <simulation scripts> pcie_ed simulation directory
synth pcie_ed.v Design example top-level HDL

<Components automatically generated by Platform Designer>

pcie_ed_tb pcie_ed_tb sim pcie_ed_tb.v Testbench including Intel FPGA BFM
<simulators> <simulation script> Testbench simulation directory
ip pcie_ed_tb DUT_pcie_tb_ip   Intel FPGA BFM (RP)
pcie_ed_tb.qsys Testbench Platform Designer file


where X= 0,1, 2, 3 (IP core numbers)

dpdk dpdk drivers net  
examples mcdma-test  
patches v20.05-rc1  
Licenses license_bsd.txt    
kernel common      
driver kmod mcdma-custom-driver Kernel driver
Licenses license_bsd.txt    
user cli perfq_app <test application software> Test Application
README Readme file
sample ref.c Reference API flow
common include regs MCDMA and Pkt Gen/Chk registers
libmqdma <user space library files> User space library
Readme     Readme file
readme Readme file
ip pcie_ed <Design example IP components>  
pcie_ed.qpf   Quartus project file
pcie_ed.qsf   Quartus setting file
pcie_ed.qsys   Design example Platform Designer file
Note: Software directory is created multiple times depending on Hard IP mode selected (1x16, 2x8 or 4x4) for Intel® Quartus® Prime Pro Edition 23.3 version onwards.
  • p0_software folder is generated for 1x16, 2x8 and 4x4 Hard IP modes.
  • p1_software folder is generated for 2x8 Hard IP modes.
  • p2_software and p3_software folders are generated for 4x4 Hard IP modes.
Note: You must use the corresponding software folder with each IP port.