Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 1/19/2024
Document Table of Contents

1.1. Terms and Acronyms

Table 1.  Acronyms
Term Definition
Avalon® -MM Avalon® Memory-Mapped Interface
Avalon® -ST Avalon® Streaming Interface
CvP Configuration via Protocol
DMA Direct Memory Access
DPDK Data Plane Development Kit
D2H Device-to-Host
D2HDM Device-to-Host Data Mover
EOF End of a File (or packet) for streaming
GCSR General Control and Status Register
HIDX Queue Head Index (pointer)
H2D Host-to-Device
H2DDM Host-to-Device Data Mover
IMMWR Immediate Write Operation
IP Intellectual Property
MCDMA Multi Channel Direct Memory Access
MRRS Maximum Read Request Size
PBA Pending Bit Array
PCIe* Peripheral Component Interconnect Express ( PCI Express* )
PD Packet Descriptor
PIO Programmed Input/Output
SOF Start of a File (or packet) for streaming
QCSR Queue Control and Status register
QID Queue Identification
TIDX Queue Tail Index (pointer)
TLP Transaction Layer Packet
UIO User Space Input/Output
VFIO Virtual Function Input/Output