Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 1/19/2024
Document Table of Contents

2.3.2. Avalon-MM PIO using MCDMA Bypass Mode

Figure 2. MCDMA IP - Avalon-MM Interface PIO Example Design using MCDMA Bypass Mode

This design example enables Avalon-MM PIO master which bypasses the DMA path. The Avalon-MM PIO master allows application to perform single, non-bursting register read/write operation with on-chip memory.

This design example only supports PIO functionality and does not perform DMA operations (similar to the design examples in Avalon-ST PIO using MCDMA Bypass Mode). Hence, the Avalon-MM DMA ports are not connected.

The design example includes the Multi Channel DMA for PCI Express IP Core with the parameters you specified and other supporting components:
  • resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode.
  • MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2.
Transfer mode option supported in test application software (perfq_app) command line:
  • PIO test: -o

For a description of which driver(s) to use with this design example, refer to Driver Support.

Note: Metadata Support is not available in AVST Interface mode, PIO using MCDMA Bypass Mode example design.
Note: User-FLR Interface is not available in AVMM Interface mode, PIO Using MCDMA Bypass Mode example design.