AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

ID 683504
Date 6/08/2018

1.1.2. Throughput for Posted Writes

The theoretical maximum throughput is calculated using the following formula:

Throughput % = payload size / (payload size + overhead)

The following figure shows the maximum throughput possible with different TLP header sizes and ignores any DLLPs and PLPs. For a 256-byte maximum payload size and a three dword TLP header (or five dword overhead), the maximum possible throughput is (256/(256+20)), or 92%.

Figure 2. Maximum Throughput for Memory Writes

The device control register (bits 7:5) in the PCI Express Configuration Space specifies maximum TLP payload size. The parameter maximum payload size sets the read-only value of the Maximum Payload Size Supported field of the Device Capabilities register (bits 2:0). The payload size you specify for your variant may be reduced based on the system maximum payload size. This maximum payload size parameter affects the resource utilization. To maximize resources, do not specify a the maximum payload size that is greater than the system maximum payload size.

PCI Express uses flow control. A TLPs is not transmitted unless the receiver has enough free buffer space to accept it. Header and data credits track available buffer space. When the application in the completer accepts the TLP, it frees the RX buffer space in the completer’s Transaction Layer. The completer sends a flow control update (FC Update DLLP) that returns the credits consumed by the originating TLP. After the device uses all of its initial credits, link bandwidth is limited by how fast it receives credit updates. Flow control updates depend on the maximum payload size and the latencies in the transmitting and receiving devices.