AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

ID 683504
Date 6/08/2018
Public
Download

1.11. Performance Benchmarking Results

The following tables list the performance of x1, and x4 operations with the Intel® Cyclone® 10 GX FPGA development board for the Intel® Xeon® E5-2603 Sandy Bridge EP processor using this reference design. The table shows the average throughput with the following parameters:
  • 100 KByte transfer
  • 20 iterations
  • A 256-byte payload
  • Maximum 512-byte read request
  • 256-byte read completion
Note: Refer to the following web page for other available reference designs and application notes for PCI Express.
Table 6.   Intel® Cyclone® 10 GX Hard IP for PCI Express Performance
Configuration DMA Read (MB/sec) DMA Write (MB/sec) Simultaneous DMA Read/Write (MB/sec) Theoretical maximum throughputs (MB/sec)
DMA Read (MB/sec) DMA Write (MB/sec)
Gen2 X4 1706 1766 1652/1446 1855 1855
Gen1 X1 223 223 214/189 231 231

Did you find the information on this page useful?

Characters remaining:

Feedback Message