AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

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ID 683504
Date 6/08/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. Project Hierarchy
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.11. Performance Benchmarking Results

The following tables list the performance of x1, and x4 operations with the Intel® Cyclone® 10 GX FPGA development board for the Intel® Xeon® E5-2603 Sandy Bridge EP processor using this reference design. The table shows the average throughput with the following parameters:
  • 100 KByte transfer
  • 20 iterations
  • A 256-byte payload
  • Maximum 512-byte read request
  • 256-byte read completion
Note: Refer to the following web page for other available reference designs and application notes for PCI Express.
Table 6.   Intel® Cyclone® 10 GX Hard IP for PCI Express Performance
Configuration DMA Read (MB/sec) DMA Write (MB/sec) Simultaneous DMA Read/Write (MB/sec) Theoretical maximum throughputs (MB/sec)
DMA Read (MB/sec) DMA Write (MB/sec)
Gen2 X4 1706 1766 1652/1446 1855 1855
Gen1 X1 223 223 214/189 231 231
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