1.11. Performance Benchmarking Results
The following tables list the performance of x1, and x4 operations with the Intel® Cyclone® 10 GX FPGA development board for the Intel® Xeon® E5-2603 Sandy Bridge EP processor using this reference design. The table shows the average throughput with the following parameters:
- 100 KByte transfer
- 20 iterations
- A 256-byte payload
- Maximum 512-byte read request
- 256-byte read completion
Note: Refer to the following web page for other available reference designs and application notes for PCI Express.
Configuration | DMA Read (MB/sec) | DMA Write (MB/sec) | Simultaneous DMA Read/Write (MB/sec) | Theoretical maximum throughputs (MB/sec) | |
---|---|---|---|---|---|
DMA Read (MB/sec) | DMA Write (MB/sec) | ||||
Gen2 X4 | 1706 | 1766 | 1652/1446 | 1855 | 1855 |
Gen1 X1 | 223 | 223 | 214/189 | 231 | 231 |
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