AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

ID 683504
Date 6/08/2018
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Document Table of Contents
Document Table of Contents
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description
1.3.1. Project Hierarchy
1.7. Hardware Installation
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.8. Running the Software Application

The software GUI has the following control fields:
  • Transfer length—Specifies the transfer length in bytes
  • Sequence—Controls the sequence for data transfer or addressing
  • Number of iterations—Controls the number of iterations for the data transfer
  • Board—Specifies the development board for the software application
  • Continuous loop—When this option is turned on, the application performs the transfer continuously
  1. Set the Transfer length to 100,000 bytes and the Sequence to Write only, Click Run.
    When set for Write only, the software programs the DMA registers in the FPGA to transfer data from the FPGA to the system memory in chunks of 100,000 bytes. The performance bars report the peak, average, and last throughput. The average throughput is computed across all the iterations.
  2. You can use the GUI to change the Transfer length and Sequence and repeat the test.
    Figure 6. Write-Only Options
  3. Double-click on the application Windows_for_AVST_On_Chip_Mem in the Windows_for_AVST_On_Chip_Mem directory.
  4. The application reports the board type, the number of active lanes, the maximum read request size, and the maximum payload size.
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